From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 21979 invoked by alias); 16 Feb 2012 15:30:35 -0000 Received: (qmail 21959 invoked by uid 22791); 16 Feb 2012 15:30:33 -0000 X-SWARE-Spam-Status: No, hits=-1.9 required=5.0 tests=AWL,BAYES_00 X-Spam-Check-By: sourceware.org Received: from hagrid.ecoscentric.com (HELO mail.ecoscentric.com) (212.13.207.197) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Thu, 16 Feb 2012 15:29:38 +0000 Received: from localhost (hagrid.ecoscentric.com [127.0.0.1]) by mail.ecoscentric.com (Postfix) with ESMTP id 0F9F12F78001 for ; Thu, 16 Feb 2012 15:29:37 +0000 (GMT) Received: from mail.ecoscentric.com ([127.0.0.1]) by localhost (hagrid.ecoscentric.com [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id Z2mGnUD54jOB; Thu, 16 Feb 2012 15:29:31 +0000 (GMT) From: bugzilla-daemon@bugs.ecos.sourceware.org To: ecos-bugs@ecos.sourceware.org Subject: [Bug 1001456] HAL misses Interrupt Clear-Pending Registers handling: wasted processing power X-Bugzilla-Reason: CC X-Bugzilla-Type: changed X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: eCos X-Bugzilla-Component: HAL X-Bugzilla-Keywords: X-Bugzilla-Severity: major X-Bugzilla-Who: ilijak@siva.com.mk X-Bugzilla-Status: UNCONFIRMED X-Bugzilla-Priority: low X-Bugzilla-Assigned-To: unassigned@bugs.ecos.sourceware.org X-Bugzilla-Target-Milestone: --- X-Bugzilla-Changed-Fields: In-Reply-To: References: X-Bugzilla-URL: http://bugs.ecos.sourceware.org/ Auto-Submitted: auto-generated Content-Type: text/plain; charset="UTF-8" MIME-Version: 1.0 Date: Thu, 16 Feb 2012 15:30:00 -0000 Message-Id: <20120216152926.47E742F78009@mail.ecoscentric.com> Mailing-List: contact ecos-bugs-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Post: List-Help: , Sender: ecos-bugs-owner@sourceware.org X-SW-Source: 2012/txt/msg00319.txt.bz2 Please do not reply to this email. Use the web interface provided at: http://bugs.ecos.sourceware.org/show_bug.cgi?id=1001456 --- Comment #15 from Ilija Kocho 2012-02-16 15:29:18 GMT --- (In reply to comment #14) > (In reply to comment #13) > > Changes to the Kernel should be done with caution. I think that this addition > > is not necessary. The desired functionality, for a given platform, can be > > introduced by #defining HAL_VAR_INTERRUPT_ACKNOWLEDGE (and/or its cousins). > > There are two problems: > > - clearing the pending interrupt bit is completely different from acknowledging > an interrupt. Acknowledgment is usually done at the end of DSR/ISR while > clearing the pending interrupt bit must be done *before* reading the peripheral > registers describing interrupt source(s): HAL_VAR_INTERRUPT_ACKNOWLEDGE is not > a solution. > > - if HAL_VAR_INTERRUPT_CLEAR_PENDING is added only to Cortex-M targets, then > how can one share a driver between an arch not requiring clearing pending > interrupt and Cortex-M cores? For instance the generic serial 16x5x driver? > Today cyg_drv_interrupt_acknowledge() resolves to CYG_EMPTY_STATEMENT for > Cortex-M, IMHO we need cyg_drv_interrupt_clear_pending() to resolve to > CYG_EMPTY_STATEMENT for non-Cortex-M, hence one can write a driver using both > cyg_drv_interrupt_acknowledge() and cyg_drv_interrupt_clear_pending() at the > correct place so the driver can work in different arch. Normally acknowledge should be enough. Regarding the IRQ re-triggering you have found out, maybe (some of) LPC17xx peripherals employ pulsed rather than level interrupts. Here is what's Cortex-M NVIC doc saying about it. http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0552a/Bhchgeei.html Then, if we must implement HAL_VAR_INTERRUPT_CLEAR_PENDING I would suggest to do it on LPC17xx variant or, if the problem appears on other variants consider Cortex-M architecture level, and avoid patching kernel files. FYI as i mentioned earlier I'll do some tests on Kinetis during next week. -- Configure bugmail: http://bugs.ecos.sourceware.org/userprefs.cgi?tab=email ------- You are receiving this mail because: ------- You are on the CC list for the bug.