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From: bugzilla-daemon@bugs.ecos.sourceware.org To: unassigned@bugs.ecos.sourceware.org Subject: [Bug 1001815] New: Freescale DSPI avoid Rx DMA if transfer fits in FIFO. Date: Thu, 04 Apr 2013 19:57:00 -0000 [thread overview] Message-ID: <bug-1001815-777@http.bugs.ecos.sourceware.org/> (raw) Please do not reply to this email, use the link below. http://bugs.ecos.sourceware.org/show_bug.cgi?id=1001815 Bug ID: 1001815 Summary: Freescale DSPI avoid Rx DMA if transfer fits in FIFO. Product: eCos Version: CVS Target: freescale_twr_k70f120m (Freescale Kinetis TWR-K70F120M board) Architecture/Host Cortex-M OS: Status: NEW Severity: enhancement Priority: low Component: Patches and contributions Assignee: unassigned@bugs.ecos.sourceware.org Reporter: ilijak@siva.com.mk CC: ecos-patches@ecos.sourceware.org Depends on: 1001814 Created attachment 2157 --> http://bugs.ecos.sourceware.org/attachment.cgi?id=2157&action=edit DSPI Rx DMA avoid Current DSPI avoids Tx DMA when transfer fits in DSPI FIFO (typically 4 bytes). The submitted patch does the same also for Rx. The benefit should be considerable especially in cached systems due to avoidance of cache invalidation. Additionally the patch implements DSPI clock gating enable as per bug 1001814. Ilija -- You are receiving this mail because: You are the assignee for the bug.
next reply other threads:[~2013-04-04 19:57 UTC|newest] Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top 2013-04-04 19:57 bugzilla-daemon [this message] 2013-04-06 12:51 ` [Bug 1001815] " bugzilla-daemon 2013-04-07 11:13 ` bugzilla-daemon 2013-04-07 16:44 ` bugzilla-daemon 2013-04-15 22:29 ` bugzilla-daemon 2013-04-15 22:31 ` bugzilla-daemon 2013-05-18 19:26 ` bugzilla-daemon 2013-05-18 19:31 ` bugzilla-daemon 2013-05-18 19:37 ` bugzilla-daemon 2013-05-18 19:41 ` bugzilla-daemon 2013-05-18 19:42 ` bugzilla-daemon 2013-06-01 22:44 ` bugzilla-daemon 2013-06-02 17:11 ` bugzilla-daemon 2013-06-02 17:11 ` bugzilla-daemon
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