From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 8506 invoked by alias); 26 Oct 2004 07:38:22 -0000 Mailing-List: contact ecos-devel-help@sources.redhat.com; run by ezmlm Precedence: bulk List-Subscribe: List-Post: List-Help: , Sender: ecos-devel-owner@sources.redhat.com Received: (qmail 8459 invoked from network); 26 Oct 2004 07:38:18 -0000 Message-ID: <000101c4bb2f$1c6f26c0$110110ac@Msicheri> Reply-To: "Sicheri Marco" From: "Sicheri Marco" To: "eCos Dev.List" References: <002401c4b848$db27a0e0$110110ac@Msicheri> Subject: Re: [ECOS] timer -> interrupt Date: Tue, 26 Oct 2004 07:38:00 -0000 Organization: CTS electronics MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="----=_NextPart_000_0024_01C4BB3F.5B867A10" X-Priority: 3 X-MSMail-Priority: Normal X-Mailer: Microsoft Outlook Express 6.00.2800.1158 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2800.1165 X-SW-Source: 2004-10/txt/msg00070.txt.bz2 This is a multi-part message in MIME format. ------=_NextPart_000_0024_01C4BB3F.5B867A10 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 7bit Content-length: 1293 Hi All, This is my code for use the timer->Interrupt I program the CPU register... so that it work only with samsung s3c44b0x... Bye and good work! Ossequi, (Best Regards/Obrigado) Marco SICHERI CTS electronics - R&D Department phone: +39 0125 235637, +39 0125 235630 e-mail: m.sicheri@ctsgroup.it http://www.ctsgroup.it ----- Original Message ----- From: "Sicheri Marco" To: "eCos Discus.List" Sent: Friday, October 22, 2004 5:07 PM Subject: [ECOS] timer -> interrupt > I All, > I need to create a timer that cause an interrupt. > Oh yes, the cyg_alarm_xxx work fine! But the resolution (tick) isn't > sufficient... :o( > My timer must count and each 100us (time between 100us and 800us) cause a > interrupt, so that my interrupt routine can work. > How can i do it? > Normaly I programming the CPU registers with time and interupt vector. But > in eCos: How do i do? > Thanks, > > Ossequi, (Best Regards/Obrigado) > Marco SICHERI > CTS electronics - R&D Department > phone: +39 0125 235637, +39 0125 235630 > e-mail: m.sicheri@ctsgroup.it > http://www.ctsgroup.it > > > -- > Before posting, please read the FAQ: http://ecos.sourceware.org/fom/ecos > and search the list archive: http://ecos.sourceware.org/ml/ecos-discuss ------=_NextPart_000_0024_01C4BB3F.5B867A10 Content-Type: application/octet-stream; name="ctstimer.c" Content-Transfer-Encoding: quoted-printable Content-Disposition: attachment; filename="ctstimer.c" Content-length: 6782 //=0A= // CTS electronics srl (www.ctsgroup.it)=0A= // Corso Vercelli, 332 - 10015 Ivrea (TORINO) Italy=0A= // All rights reserved=0A= //=0A= // Creato il: 4 Ottobre, 2004=0A= // Ultima modifica: 26 Ottobre, 2004=0A= //=0A= // Progetto: dispensatore monete=0A= //=0A= // Autore: Marco SICHERI=0A= // (m.sicheri@ctsgroup.it)=0A= //=0A= //=0A= // Made in Italy=0A= //=0A= //-------------------------------------------------------------------------= ----=0A= //=0A= // NOTE: only fo Samsung s3c44b0x=0A= //=0A= //-------------------------------------------------------------------------= ----=0A= =0A= =0A= #include "ctsinc.h"=0A= #include "../../repository/packages/hal/arm/b2/v2_0/include/hal_setting.h"= =0A= =0A= extern WORD *PDATF;=0A= =0A= =0A= ///////////////////////////////////////////////////////////////////////////= /////=0A= // Prototipi=0A= ///////////////////////////////////////////////////////////////////////////= /////=0A= void intTimer2dsr(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t d= ata);=0A= cyg_uint32 intTimer2isr(cyg_vector_t vector, cyg_addrword_t data);=0A= =0A= =0A= ///////////////////////////////////////////////////////////////////////////= /////=0A= // CPU Timer Register=0A= ///////////////////////////////////////////////////////////////////////////= /////=0A= WORD *TCON =3D (WORD *)0x1d50008; //Timer Control Register=0A= WORD *TCNTB2 =3D (WORD *)0x01d50024; //T2 Count Buffer Register=0A= WORD *TCMPB2 =3D (WORD *)0x01d50028; //T2 Compare Buffer Register=0A= WORD *TCNTO2 =3D (WORD *)0x01d5002c; //T2 Count Observation Register=0A= =0A= =0A= ///////////////////////////////////////////////////////////////////////////= /////=0A= // CPU Interupt=20=0A= ///////////////////////////////////////////////////////////////////////////= /////=0A= WORD *INTMOD =3D (WORD *)0x01e00008; //Interrupt Mode Register=0A= WORD *INTMSK =3D (WORD *)0x01e0000C; //Interrupt Mask Register=0A= WORD *I_ISPC =3D (WORD *)0x01E00024; //IRQ interrupt service pending clear = register=0A= =0A= =0A= ///////////////////////////////////////////////////////////////////////////= /////=0A= // IRQ PRIORITY=20=0A= ///////////////////////////////////////////////////////////////////////////= /////=0A= WORD *I_PSLV =3D (WORD *)0x01E00010; //IRQ PRIORITY OF SLAVE REGISTER bit 1= 1 e 10 per t2=0A= WORD *I_PMST =3D (WORD *)0x01E00014; //IRQ PRIORITY OF MASTER REGISTER bit = 11 e 10 per t2=0A= =0A= =0A= ///////////////////////////////////////////////////////////////////////////= /////=0A= // Gestione Interrupt Timer2=0A= ///////////////////////////////////////////////////////////////////////////= /////=0A= cyg_handle_t intTimer2Handle;=0A= cyg_interrupt intTimer2;=0A= cyg_sem_t data_ready;=0A= =0A= =0A= //=0A= // ----- CTSTIMERInit -------------------------------------------=0A= //=0A= BYTE CTSTIMERInit(void)=0A= {=0A= //=0A= // Impostazione routine di Interrupt per Timer2=0A= //=0A= cyg_semaphore_init(&data_ready, 0);=0A= cyg_interrupt_create(=0A= 11,=0A= 0,=0A= 0,=0A= &intTimer2isr,=0A= &intTimer2dsr,=0A= &intTimer2Handle,=0A= &intTimer2);=0A= //Attach the interupt to the vector=0A= cyg_interrupt_attach(intTimer2Handle);=0A= cyg_interrupt_unmask(intTimer2Handle);=0A= =0A= return (CPSRC_OK);=0A= }=0A= =0A= //=0A= // ----- CTSTIMERTimer2Start -------------------------------------------=0A= //=0A= void CTSTIMERTimer2Start(HWORD periodo, BOOL outSignal)=0A= //=0A= // La routine dic attura IRQ =E8 in packages/hal/arm/b2/v2_0/src/b2_misc.c= =0A= //=0A= {=0A= WORD value;=0A= =0A= //Stop=0A= (*TCON) &=3D ~BIT12;=09=0A= =0A= //Mask Timer 2=0A= (*INTMSK) |=3D BIT11;=0A= =0A= //=0A= // Programmazione Timer 2 per motore Step=0A= //=0A= (*TCNTB2) =3D periodo; //Periodo=0A= (*TCMPB2) =3D 0; //compare value=0A= =0A= if (outSignal =3D=3D TRUE)=0A= {=0A= //CPU timer2 out toggle=0A= WORD *PCONE =3D (WORD *)0x01D20028; //Port E Control=0A= *PCONE |=3D BIT11;=0A= *PCONE &=3D ~BIT10;=0A= }=0A= =0A= //Set T2 Interrupt Mode=0A= (*INTMOD) &=3D ~BIT11; // =3D IRQ=0A= =0A= //Unmask Timer 2=0A= (*INTMSK) &=3D ~BIT11;=0A= =0A= //Set Priority=0A= // (*I_PSLV) &=3D ~(BIT11 | BIT10); //se la tocco non funziona pi=F9=0A= // (*I_PMST) &=3D ~(BIT11 | BIT10);=0A= =0A= //=0A= // NOTE: deve essere questa la sequenza, altrimenti non funziona....=0A= //=0A= =0A= //Set T2 mode=0A= value =3D (*TCON);=0A= value |=3D BIT15; //Autoreload ON=0A= value &=3D ~BIT14; //inverter OFF=0A= value |=3D BIT13; //Update cnt ON=0A= (*TCON) =3D value;=0A= =0A= value =3D (*TCON);=0A= value &=3D ~(BIT12 | BIT13 | BIT14 | BIT15);=09=0A= value |=3D (BIT12 | BIT15); //Start + Autoreload=0A= (*TCON) =3D value; //Start + Autoreload=0A= }=0A= =0A= //=0A= // ----- CTSTIMERBreakTimer2 -------------------------------------------=0A= //=0A= void CTSTIMERTimer2Stop(void)=0A= {=0A= (*TCON) &=3D ~BIT12; //Stop=0A= =0A= //Mask Timer 2=0A= (*INTMSK) |=3D BIT11;=0A= }=0A= =0A= //=0A= // ----- intTimer2isr --------------------------------=0A= //=0A= cyg_uint32 intTimer2isr(cyg_vector_t vector, cyg_addrword_t data)=0A= {=0A= //Tell the processor that we have received=0A= //the interrupt=0A= cyg_interrupt_acknowledge(vector);=0A= =0A= //=0A= // my code=0A= //=0A= //@ debug only move the IO=0A= (*PDATF) |=3D BIT4;=0A= (*PDATF) &=3D ~BIT4;=0A= =0A= //Block this interrupt from occurring until=0A= //the DSR completes=0A= cyg_interrupt_mask(vector);=0A= =0A= //Tell the kernel that chained interrupt processing=20=0A= //is done and the DSR needs to be executed next=0A= return (CYG_ISR_HANDLED | CYG_ISR_CALL_DSR);=0A= }=0A= =0A= //=0A= // ----- intTimer2dsr --------------------------------=0A= //=0A= void intTimer2dsr(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t d= ata)=0A= {=0A= //signal the thread to run for further processing=0A= cyg_semaphore_post(&data_ready);=0A= =0A= //allow this interrupt to occur again=0A= cyg_interrupt_unmask(vector);=0A= }=0A= =0A= /////////////////////////////////// END ///////////////////////////////////= /////=0A= =0A= /*=0A= //=0A= // ----- intTimer2isr --------------------------------=0A= //=0A= cyg_uint32 intTimer2isr(cyg_vector_t vector, cyg_addrword_t data)=0A= {=0A= //Block this interrupt from occurring until=0A= //the DSR completes=0A= cyg_interrupt_mask(vector);=0A= =0A= //Tell the processor that we have received=0A= //the interrupt=0A= cyg_interrupt_acknowledge(vector);=0A= =09=0A= //=0A= // my code=0A= //=0A= (*PDATF) |=3D BIT4;=0A= (*PDATF) &=3D ~BIT4;=0A= =0A= //Tell the kernel that chained interrupt processing=20=0A= //is done and the DSR needs to be executed next=0A= return (CYG_ISR_HANDLED | CYG_ISR_CALL_DSR);=0A= }=0A= */= ------=_NextPart_000_0024_01C4BB3F.5B867A10--