MMU enabling for IXP425

MMU enabling for IXP425

[Raghu]

Hi, 
I have a IXP425 based custom board, and trying to
enable MMU in Redboot ROM monitor. I have 64 Mb SDRAM.
And set following mem map in "hal_platform_extras.h"

VA          PA         XCB  Size   Desc
0x00000000  0x00000000 010  64Mb   SDRAM ( Cached )
0x10000000  0x10000000 010  64Mb   SDRAM ( Alias )
0x20000000  0x00000000 000  64Mb   SDRAM ( UnCached )
Reset as in IXDP425 !
-----------------------------------------------------
mmu_table:
// 64MB SDRAM
.set	__base, 0x000
.rept	 0x040 - 0x000
FL_SECTION_ENTRY __base, 0, 3, 0, 0, 1, 0
.set	__base, __base + 1
.endr
// 192MB Unused
.rept 0x100 - 0x040
.word 0
.set	__base, __base + 1
.endr

// 64MB SDRAM Alias
.rept	 0x140 - 0x100
FL_SECTION_ENTRY __base, 0, 3, 0, 0, 1, 0
.set	__base, __base + 1
.endr

// 192MB Unused
.rept	 0x200 - 0x140
.word 0
.set	__base, __base + 1
.endr

// 64MB SDRAM (uncached)
.set	__base, 0x000
.rept	 0x240 - 0x200
FL_SECTION_ENTRY __base, 0, 3, 0, 0, 0, 0
.set	__base, __base + 1
.endr

// 192MB Unused
.set	__base, 0x240
.rept	 0x300 - 0x240
.word 0
.set	__base, __base + 1
.endr
-----------------------------------------------------
But in the "hal_platform_setup.h" file on enabling the
DCache at instruction, "mrc p15, 0, r0, c1, c0, 0" is
get a "Prefetch Abort".

// enable mmu
mrc	p15, 0, r0, c1, c0, 0
orr	r0, r0, #MMU_Control_M
orr	r0, r0, #MMU_Control_R
mcr	p15, 0, r0, c1, c0, 0
CPWAIT	r0
// enable D cache
mrc     p15, 0, r0, c1, c0, 0
orr     r0, r0, #MMU_Control_C
mcr     p15, 0, r0, c1, c0, 0
CPWAIT  r0

Any clues ? 
Also how are the FL_SECTION_ENTRY for PCI, MISC
created. The macro uses on .word everytime.

Regards
Raghu




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Re: MMU enabling for IXP425

[Mark Salter]

On Wed, 2005-01-26 at 03:26 -0800, Raghu wrote:
> Hi, 
> I have a IXP425 based custom board, and trying to
> enable MMU in Redboot ROM monitor. I have 64 Mb SDRAM.
> And set following mem map in "hal_platform_extras.h"
> 
> VA          PA         XCB  Size   Desc
> 0x00000000  0x00000000 010  64Mb   SDRAM ( Cached )
> 0x10000000  0x10000000 010  64Mb   SDRAM ( Alias )
> 0x20000000  0x00000000 000  64Mb   SDRAM ( UnCached )
> Reset as in IXDP425 !
...
> But in the "hal_platform_setup.h" file on enabling the
> DCache at instruction, "mrc p15, 0, r0, c1, c0, 0" is
> get a "Prefetch Abort".
> 
...
> Any clues ? 
> Also how are the FL_SECTION_ENTRY for PCI, MISC
> created. The macro uses on .word everytime.
> 
I would look carefully at the page table. The way the table is
constructed in hal_platform_extras.h is error prone. The latest
code in cvs uses a less error prone method. I suspect that there
is no mapping for the flash and the first i-fetch after mmu is
enabled is causing the prefetch abort.

The pagetable entries for PCI and other IO areas should be there
in hal_platform_extras.h

--Mark