From: Errin Bechtel <errin_bechtel@yahoo.com>
To: ecos-devel@sources.redhat.com
Subject: patch to add support for MCF5282 support
Date: Wed, 13 Apr 2005 13:39:00 -0000 [thread overview]
Message-ID: <20050413133831.50056.qmail@web61002.mail.yahoo.com> (raw)
Here is a patch to add support for the mcf5282.
Errin Bechtel
Index:
packages/hal/m68k/mcf52xx/mcf5282/proc/current/cdl/hal_m68k_mcf52xx_mcf5282.cdl
===================================================================
RCS file:
packages/hal/m68k/mcf52xx/mcf5282/proc/current/cdl/hal_m68k_mcf52xx_mcf5282.cdl
diff -N
packages/hal/m68k/mcf52xx/mcf5282/proc/current/cdl/hal_m68k_mcf52xx_mcf5282.cdl
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++
packages/hal/m68k/mcf52xx/mcf5282/proc/current/cdl/hal_m68k_mcf52xx_mcf5282.cdl
1 Jan 1970 00:00:00 -0000
@@ -0,0 +1,62 @@
+#
====================================================================
+#
+# hal_m68k_mcf52xx_mcf5282.cdl
+#
+# M68K/MCF5282 variant architectural HAL package
configuration data
+#
+#
====================================================================
+#####ECOSGPLCOPYRIGHTBEGIN####
+## -------------------------------------------
+## This file is part of eCos, the Embedded
Configurable Operating System.
+## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red
Hat, Inc.
+##
+## eCos is free software; you can redistribute it
and/or modify it under
+## the terms of the GNU General Public License as
published by the Free
+## Software Foundation; either version 2 or (at your
option) any later version.
+##
+## eCos is distributed in the hope that it will be
useful, but WITHOUT ANY
+## WARRANTY; without even the implied warranty of
MERCHANTABILITY or
+## FITNESS FOR A PARTICULAR PURPOSE. See the GNU
General Public License
+## for more details.
+##
+## You should have received a copy of the GNU General
Public License along
+## with eCos; if not, write to the Free Software
Foundation, Inc.,
+## 59 Temple Place, Suite 330, Boston, MA 02111-1307
USA.
+##
+## As a special exception, if other files instantiate
templates or use macros
+## or inline functions from this file, or you compile
this file and link it
+## with other works to produce a work based on this
file, this file does not
+## by itself cause the resulting work to be covered
by the GNU General Public
+## License. However the source code for this file
must still be made available
+## in accordance with section (3) of the GNU General
Public License.
+##
+## This exception does not invalidate any other
reasons why a work based on
+## this file might be covered by the GNU General
Public License.
+##
+## Alternative licenses for eCos may be arranged by
contacting Red Hat, Inc.
+## at http://sources.redhat.com/ecos/ecos-license/
+## -------------------------------------------
+#####ECOSGPLCOPYRIGHTEND####
+#
====================================================================
+
+cdl_package CYGPKG_HAL_M68K_MCF52xx_MCF5282 {
+ display "mcf5282 68k/Coldfire variant
HAL"
+ parent CYGPKG_HAL_M68K_MCF52xx
+ requires CYGPKG_HAL_M68K_MCF52xx
+ implements CYGINT_HAL_M68K_VARIANT
+ hardware
+ include_dir cyg/hal
+ define_header hal_m68k_mcf52xx_mcf5282.h
+
+ description "The mcf5282 68k/Coldfire
variant HAL package provides
+ generic support for this processor
architecture. It is also
+ necessary to select a specific target
platform HAL package."
+
+ define_proc {
+ puts $::cdl_header "#include
<pkgconf/hal_m68k_mcf52xx.h>"
+ }
+
+ compile proc_startup.c proc_arch.S
proc_intr.c proc_misc.c memcpy.c
+
+}
+
Index:
packages/hal/m68k/mcf52xx/mcf5282/proc/current/include/mcf5282_sim.h
===================================================================
RCS file:
packages/hal/m68k/mcf52xx/mcf5282/proc/current/include/mcf5282_sim.h
diff -N
packages/hal/m68k/mcf52xx/mcf5282/proc/current/include/mcf5282_sim.h
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++
packages/hal/m68k/mcf52xx/mcf5282/proc/current/include/mcf5282_sim.h
1 Jan 1970 00:00:00 -0000
@@ -0,0 +1,874 @@
+#ifndef MCF5282_SIM_H
+#define MCF5282_SIM_H
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded
Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red
Hat, Inc.
+//
+// eCos is free software; you can redistribute it
and/or modify it under
+// the terms of the GNU General Public License as
published by the Free
+// Software Foundation; either version 2 or (at your
option) any later version.
+//
+// eCos is distributed in the hope that it will be
useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of
MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU
General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General
Public License along
+// with eCos; if not, write to the Free Software
Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307
USA.
+//
+// As a special exception, if other files instantiate
templates or use macros
+// or inline functions from this file, or you compile
this file and link it
+// with other works to produce a work based on this
file, this file does not
+// by itself cause the resulting work to be covered
by the GNU General Public
+// License. However the source code for this file
must still be made available
+// in accordance with section (3) of the GNU General
Public License.
+//
+// This exception does not invalidate any other
reasons why a work based on
+// this file might be covered by the GNU General
Public License.
+//
+// Alternative licenses for eCos may be arranged by
contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+
+/*
+
+ Defines for the mcf5282 System Integration Module
(SIM)
+
+*/
+
+#include <pkgconf/hal.h>
+#include <cyg/infra/cyg_type.h>
+
+typedef struct { /* system control module */
+ u32_t ipsbar; /* 00->03 ips base address register*/
+ u32_t rambar; /* 04->07 processor-local memory base
address register */
+ u32_t flashbar; /* 08->0b */
+ u8_t pack00[4]; /* 0c->0f */
+ u8_t crsr; /* 10 core reset status register */
+ u8_t cwcr; /* 11 core watchdog control register */
+ u8_t lpicr; /* 12 */
+ u8_t cwsr; /* 13 core watchdog service register */
+ u32_t dmareqc; /* 14->17 dma request control
register */
+ u8_t pack01[4]; /* 18->1b */
+ u32_t mpark; /* 1c->1f system bus master
arbitration programming model */
+ u8_t mpr; /* 20 master privilege register */
+ u8_t pack02[3]; /* 21-23 */
+ u8_t pacr0; /* 24 peripheral access control
registers(0-8) */
+ u8_t pacr1; /* 25 */
+ u8_t pacr2; /* 26 */
+ u8_t pacr3; /* 27 */
+ u8_t pacr4; /* 28 */
+ u8_t pack03; /* 29 */
+ u8_t pacr5; /* 2a */
+ u8_t pacr6; /* 2b */
+ u8_t pacr7; /* 2c */
+ u8_t pack04; /* 2d */
+ u8_t pacr8; /* 2e */
+ u8_t pack05; /* 2f */
+ u8_t gpacr0; /* 30 grouped peripheral access
control registers(0-1) */
+ u8_t gpacr1; /* 31 */
+ u8_t pack06[14]; /* 32->3f */
+} scmstruct;
+
+#define MCF5282_SDRAM_DCR_NAM 0x2000 // No address
multiplexing.
+#define MCF5282_SDRAM_DCR_COC 0x1000 // Command on
SDRAM clock enable (SCKE).
+#define MCF5282_SDRAM_DCR_IS 0x0800 // Initiate
self-refresh command.
+#define MCF5282_SDRAM_DCR_RTIM1 0x0400 // Refresh
timing.
+#define MCF5282_SDRAM_DCR_RTIM0 0x0200
+#define MCF5282_SDRAM_DCR_RC8 0x0100 // Refresh
count.
+#define MCF5282_SDRAM_DCR_RC7 0x0080
+#define MCF5282_SDRAM_DCR_RC6 0x0040
+#define MCF5282_SDRAM_DCR_RC5 0x0020
+#define MCF5282_SDRAM_DCR_RC4 0x0010
+#define MCF5282_SDRAM_DCR_RC3 0x0008
+#define MCF5282_SDRAM_DCR_RC2 0x0004
+#define MCF5282_SDRAM_DCR_RC1 0x0002
+#define MCF5282_SDRAM_DCR_RC0 0x0001
+
+#define MCF5282_SDRAM_DACR_RE 0x8000 // Refresh
enable.
+#define MCF5282_SDRAM_DACR_CASL1 0x2000 // CAS
latency.
+#define MCF5282_SDRAM_DACR_CASL0 0x1000
+#define MCF5282_SDRAM_DACR_CBM2 0x0400 // Command
and bank MUX [2:0].
+#define MCF5282_SDRAM_DACR_CBM1 0x0200
+#define MCF5282_SDRAM_DACR_CBM0 0x0100
+#define MCF5282_SDRAM_DACR_IMRS 0x0040 // Initiate
mode register set (MRS) command.
+#define MCF5282_SDRAM_DACR_PS1 0x0020 // Port size.
+#define MCF5282_SDRAM_DACR_PS0 0x0010
+#define MCF5282_SDRAM_DACR_IP 0x0008 // Initiate
precharge all (PALL) command.
+
+#define MCF5282_SDRAM_DMR_WP 0x0100 // Write
protect.
+#define MCF5282_SDRAM_DMR_AM5 0x0040 // Address
modifier masks.
+#define MCF5282_SDRAM_DMR_AM4 0x0020
+#define MCF5282_SDRAM_DMR_AM3 0x0010
+#define MCF5282_SDRAM_DMR_AM2 0x0008
+#define MCF5282_SDRAM_DMR_AM1 0x0004
+#define MCF5282_SDRAM_DMR_AM0 0x0002
+#define MCF5282_SDRAM_DMR_V 0x0001 // Valid.
+
+typedef struct { /* synchronous dram */
+ u16_t dcr; /* 40->41 dram control register */
+ u8_t pack00[6]; /* 42->47 */
+ u32_t dacr0; /* 48->4b dram address and control
registers(0-1) */
+ u32_t dmr0; /* 4c->4f dram mask registers(0-1) */
+ u32_t dacr1; /* 50->53 */
+ u32_t dmr1; /* 54->57 */
+} sdramcstruct;
+
+/* ------------- will become array cs[8] 0080->00df
---------------- */
+typedef struct { /* chip-select */
+ u16_t csar; /* 16bit chip-select address register
*/
+ u8_t pack00[2]; /* 16bit reserved */
+ u32_t csmr; /* 32bit chip-select mask register */
+ u8_t pack01[2]; /* 16bit reserved */
+ u16_t cscr; /* 16bit chip-select control register
*/
+} csstruct;
+
+
+/* ------------- will become array dma[4] 0100->01d0
--------------- */
+typedef struct { /* dma controller modules */
+ u32_t sar; /* 32bit source address register */
+ u32_t dar; /* 32bit destination address register */
+ u32_t dcr; /* 32bit dma controller register */
+ u8_t pack00[3]; /* 24bit reserved */
+ u32_t bcr; /* 32bit byte count register */
+ u8_t dsr; /* dma status register */
+ u8_t pack01[3]; /* 24bit reserved */
+ u8_t pack02[40];
+} dmastruct;
+
+/* ------------- will become array uart[3] 0200->02bc
--------------- */
+
+#define MCF5282_UART_UMR1_RXRTS (0x80)
+#define MCF5282_UART_UMR1_RXIRQ (0x40)
+#define MCF5282_UART_UMR1_ERR (0x20)
+#define MCF5282_UART_UMR1_PM_MULTI_ADDR (0x1C)
+#define MCF5282_UART_UMR1_PM_MULTI_DATA (0x18)
+#define MCF5282_UART_UMR1_PM_NONE (0x10)
+#define MCF5282_UART_UMR1_PM_FORCE_HI (0x0C)
+#define MCF5282_UART_UMR1_PM_FORCE_LO (0x08)
+#define MCF5282_UART_UMR1_PM_ODD (0x04)
+#define MCF5282_UART_UMR1_PM_EVEN (0x00)
+#define MCF5282_UART_UMR1_BC_5 (0x00)
+#define MCF5282_UART_UMR1_BC_6 (0x01)
+#define MCF5282_UART_UMR1_BC_7 (0x02)
+#define MCF5282_UART_UMR1_BC_8 (0x03)
+
+#define MCF5282_UART_UMR2_CM_NORMAL (0x00)
+#define MCF5282_UART_UMR2_CM_ECHO (0x40)
+#define MCF5282_UART_UMR2_CM_LOCAL_LOOP (0x80)
+#define MCF5282_UART_UMR2_CM_REMOTE_LOOP (0xC0)
+#define MCF5282_UART_UMR2_TXRTS (0x20)
+#define MCF5282_UART_UMR2_TXCTS (0x10)
+#define MCF5282_UART_UMR2_STOP_BITS_1 (0x07)
+#define MCF5282_UART_UMR2_STOP_BITS_15 (0x08)
+#define MCF5282_UART_UMR2_STOP_BITS_2 (0x0F)
+
+#define MCF5282_UART_USR_RB (0x80)
+#define MCF5282_UART_USR_FE (0x40)
+#define MCF5282_UART_USR_PE (0x20)
+#define MCF5282_UART_USR_OE (0x10)
+#define MCF5282_UART_USR_TXEMP (0x08)
+#define MCF5282_UART_USR_TXRDY (0x04)
+#define MCF5282_UART_USR_FFULL (0x02)
+#define MCF5282_UART_USR_RXRDY (0x01)
+
+#define MCF5282_UART_UCR_NONE (0x00)
+#define MCF5282_UART_UCR_STOP_BREAK (0x70)
+#define MCF5282_UART_UCR_START_BREAK (0x60)
+#define MCF5282_UART_UCR_RESET_BKCHGINT (0x50)
+#define MCF5282_UART_UCR_RESET_ERROR (0x40)
+#define MCF5282_UART_UCR_RESET_TX (0x30)
+#define MCF5282_UART_UCR_RESET_RX (0x20)
+#define MCF5282_UART_UCR_RESET_MR (0x10)
+#define MCF5282_UART_UCR_TX_DISABLED (0x08)
+#define MCF5282_UART_UCR_TX_ENABLED (0x04)
+#define MCF5282_UART_UCR_RX_DISABLED (0x02)
+#define MCF5282_UART_UCR_RX_ENABLED (0x01)
+
+#define MCF5282_UART_UIPCR_COS (0x10)
+#define MCF5282_UART_UIPCR_CTS (0x01)
+
+#define MCF5282_UART_UACR_BRG (0x80)
+#define MCF5282_UART_UACR_CTMS_TIMER (0x60)
+#define MCF5282_UART_UACR_IEC (0x01)
+
+#define MCF5282_UART_UISR_COS (0x80)
+#define MCF5282_UART_UISR_DB (0x04)
+#define MCF5282_UART_UISR_RXRDY (0x02)
+#define MCF5282_UART_UISR_TXRDY (0x01)
+
+#define MCF5282_UART_UIMR_COS (0x80)
+#define MCF5282_UART_UIMR_DB (0x04)
+#define MCF5282_UART_UIMR_FFULL (0x02)
+#define MCF5282_UART_UIMR_TXRDY (0x01)
+
+#define MCF5282_UART_UCSR_RXCLKTIMER 0xd0 /* RX
clock is timer */
+#define MCF5282_UART_UCSR_RXCLKEXT16 0xe0 /* RX
clock is external x16 */
+#define MCF5282_UART_UCSR_RXCLKEXT1 0xf0 /* RX clock
is external x1 */
+
+#define MCF5282_UART_UCSR_TXCLKTIMER 0x0d /* TX
clock is timer */
+#define MCF5282_UART_UCSR_TXCLKEXT16 0x0e /* TX
clock is external x16 */
+#define MCF5282_UART_UCSR_TXCLKEXT1 0x0f /* TX clock
is external x1 */
+
+typedef struct
+{
+ u8_t umr; /* UARTx Mode Register, 8-bit,
R/W (00) */
+ u8_t pack01[3]; /* 01-03 */
+ u8_t usr; /* UARTx Status Register, 8-bit,
R (04) */
+ u8_t pack02[7]; /* 05-0B */
+ u8_t urbuf; /* UARTx Receiver Buffer, 8-bit,
R (0C) */
+ u8_t pack03[3]; /* 0D-0F */
+ u8_t uipcr; /* UARTx Input Port Change
Register, 8-bit, R (10) */
+ u8_t pack04[3]; /* 11-13 */
+ u8_t uisr; /* UARTx Interrupt Status
Register, 8-bit, R (14) */
+ u8_t pack05[3]; /* 15-17 */
+ u8_t ubg1; /* UARTx Baud Rate Generator
PreScale MSB, 8-bit, R/W (18) */
+ u8_t pack06[3]; /* 19-1B */
+ u8_t ubg2; /* UARTx Baud Rate Generator
PreScale LSB, 8-bit, R/W (1C) */
+ u8_t pack07[19]; /* 1D-2F */
+ u8_t uivr; /* UARTx Interrupt Vector
Register, 8-bit, R/W (30) */
+ u8_t pack08[3]; /* 31-33 */
+ u8_t uip; /* UARTx Input Port Register,
8-bit, R (34) */
+} UARTReadStruct;
+
+typedef struct
+{
+ u8_t umr; /* UARTx Mode Register, 8-bit,
R/W (00) */
+ u8_t pack01[3]; /* 01-03 */
+ u8_t ucsr; /* UART1 Clock Select Register,
8-bit, W (04) */
+ u8_t pack02[3]; /* 05-07 */
+ u8_t ucr; /* UARTx Command Register,
8-bit, W (08) */
+ u8_t pack2a[3]; /* 09-0B */
+ u8_t utbuf; /* UARTx Transmitter Buffer,
8-bit, W (0C) */
+ u8_t pack03[3]; /* 0D-0F */
+ u8_t uacr; /* UARTx Auxiliary Control
Register, 8-bit, W (10) */
+ u8_t pack04[3]; /* 11-13 */
+ u8_t uimr; /* UARTx Interrupt Mask
Register, 8-bit, W (14) */
+ u8_t pack05[3]; /* 15-17 */
+ u8_t ubg1; /* UARTx Baud Rate Generator
PreScale MSB, 8-bit, R/W (18) */
+ u8_t pack06[3]; /* 19-1B */
+ u8_t ubg2; /* UARTx Baud Rate Generator
PreScale LSB, 8-bit, R/W (1C) */
+ u8_t pack07[19]; /* 1D-2F */
+ u8_t uivr; /* UARTx Interrupt Vector
Register, 8-bit, R/W (30) */
+ u8_t pack08[7]; /* 31-37 */
+ u8_t uop1; /* UARTx Output Port Bit Set
Command, 8-bit, W (38) */
+ u8_t pack09[3]; /* 39-3B */
+ u8_t uop0; /* UARTx Output Port Bit Reset
Command, 8-bit, W (3C) */
+} UARTWriteStruct;
+
+typedef union
+{
+ UARTReadStruct read;
+ UARTWriteStruct write;
+ u8_t pack01[0x40];
+} uartstruct;
+
+typedef struct { /* i2c module */
+ u8_t adr; /* 0300 address register */
+ u8_t pack00[3]; /* 0301->0303 */
+ u8_t fdr; /* 0304 frequency divider register */
+ u8_t pack01[3]; /* 0305->0307 */
+ u8_t cr; /* 0308 control register */
+ u8_t pack02[3]; /* 0309-030b */
+ u8_t sr; /* 030c status register */
+ u8_t pack03[3]; /* 030d->030f */
+ u8_t dr; /* 0310 data i/o register */
+ u8_t pack04[3]; /* 0311->0313 */
+} i2cstruct;
+
+typedef struct /* qspi module */
+{
+ u16_t qmr; /* 0340->0341 mode register */
+ u8_t pack00[2]; /* 0342->0343 */
+ u16_t qdlyr; /* 0344->0345 delay register */
+ u8_t pack01[2]; /* 0346->0347 */
+ u16_t qwr; /* 0348->0349 wrap register */
+ u8_t pack02[2]; /* 034a->034b */
+ u16_t qir; /* 034c->034d interrupt register */
+ u8_t pack03[2]; /* 034e->034f */
+ u16_t qar; /* 0350->0351 address register */
+ u8_t pack04[2]; /* 0352->0353 */
+ u16_t qdr; /* 0354->0355 data register */
+ u8_t pack05[2]; /* 0356->0357 */
+} qspistruct;
+
+/* ------------- will become array timer[4]
0400->04cc --------------- */
+typedef struct { /* dma timers */
+ u16_t tmr; /* 0400->0401 mode register */
+ u8_t txmr; /* 0402 extended mode register */
+ u8_t ter; /* 0403 event register */
+ u32_t trr; /* 0404->0407 reference register */
+ u32_t tcr; /* 0408->040b capture register */
+ u32_t tcn; /* 040c->040f counter register */
+ u8_t pack00[48]; /* 0410->047f */
+} dmatimerstruct;
+
+#define MCF5282_INTC_IMRL_MASKALL 0x0001
+
+typedef struct /* interrupt controller module */
+{
+ u32_t iprh; /* 0c00->0c03 pending register high */
+ u32_t iprl; /* 0c04->0c07 pending register low */
+ u32_t imrh; /* 0c08->0c0b mask register high */
+ u32_t imrl; /* 0c0c->0c0f mask register low */
+ u32_t intfrch; /* 0c10->0c13 force register high */
+ u32_t intfrcl; /* 0c14->0c17 force register low */
+ u8_t irlr; /* 0c18 request level register */
+ u8_t iacklpr; /* 0c19 acknowledge level and priority
register */
+ u8_t pack01[38]; /* 0c1a->0c3f */
+ u8_t icrn[64];
+ u8_t pack03[96]; /* 0c7f->0cdf */
+ u8_t swackr; /* 0ce0 software ack register*/
+ u8_t pack04[3]; /* 0ce1->0ce3 */
+ u8_t l1ackr; /* 0ce4 level ack registers(1-7) */
+ u8_t pack05[3]; /* 0ce5->0ce7 */
+ u8_t l2ackr; /* 0ce8 */
+ u8_t pack06[3]; /* 0ce9->0ceb */
+ u8_t l3ackr; /* 0cec */
+ u8_t pack07[3]; /* 0ced->0cef */
+ u8_t l4ackr; /* 0cf0 */
+ u8_t pack08[3]; /* 0cf1->0cf3 */
+ u8_t l5ackr; /* 0cf4 */
+ u8_t pack09[3]; /* 0cf5->0cf7 */
+ u8_t l6ackr; /* 0cf8 */
+ u8_t pack10[3]; /* 0cf9->0cfb */
+ u8_t l7ackr; /* 0cfc */
+ u8_t pack11[3]; /* 0cfd->0cff */
+} intcstruct;
+
+typedef struct { /* global interrupt acknowledge
cycle module */
+
+ u8_t gswackr; /* 0fe0->0fe0 global software
interrupt acknowledge register */
+ u8_t pack00[3]; /* 0fe1->0fe3 */
+ u8_t gl1iackr; /* 0fe4->0fe4 global level 1
interrupt acknowledge register */
+ u8_t pack01[3]; /* 0fe5->0fe7 */
+ u8_t gl2iackr; /* 0fe8->0fe8 global level 2
interrupt acknowledge register */
+ u8_t pack02[3]; /* 0fe9->0feb */
+ u8_t gl3iackr; /* 0fec->0fec global level 3
interrupt acknowledge register */
+ u8_t pack03[3]; /* 0fed->0fef */
+ u8_t gl4iackr; /* 0ff0->0ff0 global level 4
interrupt acknowledge register */
+ u8_t pack04[3]; /* 0ff1->0ff3 */
+ u8_t gl5iackr; /* 0ff4->0ff4 global level 5
interrupt acknowledge register */
+ u8_t pack05[3]; /* 0ff5->0ff7 */
+ u8_t gl6iackr; /* 0ff8->0ff8 global level 6
interrupt acknowledge register */
+ u8_t pack06[3]; /* 0ff9->0ffb */
+ u8_t gl7iackr; /* 0ffc->0ffc global level 7
interrupt acknowledge register */
+ u8_t pack07[3]; /* 0ffc->0fff */
+
+} giacstruct;
+
+typedef struct { /* fast ethernet controller */
+ u32_t eir; /* 1004->1007 interrupt event register
*/
+ u32_t eimr; /* 1008->100b interrupt mask register
*/
+ u8_t pack00[4]; /* 100c->100f */
+ u32_t rdar; /* 1010->1013 recieve descriptor active
register */
+ u32_t tdar; /* 1014->1017 transmit descriptor
active register */
+ u8_t pack01[12]; /* 1018->1023 */
+ u32_t ecr; /* 1024->1027 ethernet control register
*/
+ u8_t pack02[24]; /* 1028->103f */
+ u32_t mdata; /* 1040->1043 mii data register */
+ u32_t mscr; /* 1044->1047 mii speed control
register */
+ u8_t pack03[28]; /* 1048->1063 */
+ u32_t mibc; /* 1064->1067 mib control/status
register */
+ u8_t pack04[28]; /* 1068->1083 */
+ u32_t rcr; /* 1084->1087 recieve control register
*/
+ u8_t pack05[60]; /* 1088->10c3 */
+ u32_t tcr; /* 10c4->10c7 transmit control register
*/
+ u8_t pack06[28]; /* 10c8->10e3 */
+ u32_t palr; /* 10e4->10e7 physical address low
register */
+ u32_t paur; /* 10e8->10eb physical address high+
type field */
+ u32_t opd; /* 10ec->10ef opcode + pause duration */
+ u8_t pack07[40]; /* 10f0->1117 */
+ u32_t iaur; /* 1118->111b upper 32bits of
individual hash table */
+ u32_t ialr; /* 111c->111f lower 32bits of
individual hash table */
+ u32_t gaur; /* 1120->1123 upper 32bits of group
hash table */
+ u32_t galr; /* 1124->1127 lower 32bits of group
hash table */
+ u8_t pack08[28]; /* 1128->1143 */
+ u32_t tfwr; /* 1144->1147 transmit fifo watermark
*/
+ u8_t pack09[4]; /* 1148->114b */
+ u32_t frbr; /* 114c->114f fifo receive bound
register */
+ u32_t frsr; /* 1150->1153 fifo receive fifo start
registers */
+ u8_t pack10[44]; /* 1154->117f */
+ u32_t erdsr; /* 1180->1183 pointer to receive
descriptor ring */
+ u32_t etdsr; /* 1184->1187 pointer to transmit
descriptor ring */
+ u32_t emrbr; /* 1188->118b maximum receive buffer
size */
+} fecstruct;
+
+typedef struct { /* fec, rmon transmit */
+ u32_t drop; /* 1200->1203 count of frames not
counted correctly */
+ u32_t packets; /* 1204->1207 packet count */
+ u32_t bc_pkt; /* 1208->120b broadcast packets */
+ u32_t mc_pkt; /* 120c->120f multicast packets */
+ u32_t crc_align; /* 1200->1213 packets with
crc/align error */
+ u32_t undersize; /* 1214->1217 packets < 64 bytes,
good crc */
+ u32_t oversize; /* 1218->121b packets > max_fl
bytes, good crc */
+ u32_t frag; /* 121c->121f packets < 64 bytes, bad
crc */
+ u32_t jab; /* 1220->1223 packets > max_fl bytes,
bad crc */
+ u32_t col; /* 1224->1227 collision count */
+ u32_t p64; /* 1228->122b 64 byte packets */
+ u32_t p65to127; /* 122c->122f 65 to 127 byte packets
*/
+ u32_t p128to255; /* 1230->1233 128 to 255 byte
packets */
+ u32_t p256to511; /* 1234->1237 256 to 511 byte
packets */
+ u32_t p512to1023; /* 1238->123b 512 to 1023 byte
packets */
+ u32_t p1024to2047; /* 123c->123f 1024 to 2047 byte
packets */
+ u32_t p_gte2048; /* 1230->1243 > 2048 byte packets
*/
+ u32_t octets; /* 1244->1247 octets */
+} fec_rmon_tstruct;
+
+typedef struct { /* fec, ieee transmit */
+ u32_t drop; /* 1248->124b count of frames not
counted correctly */
+ u32_t frame_ok; /* 124c->124f frames transmitted ok
*/
+ u32_t scol; /* 1250->1253 frames transmitted with
single collision */
+ u32_t mcol; /* 1254->1257 frames transmitted with
multiple collisions*/
+ u32_t def; /* 1258->125b frames transmitted after
deferral delay */
+ u32_t lcol; /* 125c->125f frames transmitted with
late collision */
+ u32_t excol; /* 1260->1263 frames transmitted with
excessive collisions */
+ u32_t macerr; /* 1264->1267 frames transmitted with
tx fifo underrun */
+ u32_t cserr; /* 1268->126b frames transmitted with
carrier sense error */
+ u32_t sqe; /* 126c->126f frames transmitted with
sqe error */
+ u32_t fdxfc; /* 1270->1273 flow control pause
frames trasmitted */
+ u32_t octets_ok; /* 1274->1277 octet count for
frames transmitted w/o error */
+} fec_ieee_tstruct;
+
+typedef struct { /* fec, rmon receive */
+ u32_t packets; /* 1284->1287 packet count */
+ u32_t bc_pkt; /* 1288->128b broadcast packets */
+ u32_t mc_pkt; /* 128c->128f multicast packets */
+ u32_t crc_align; /* 1290->1293 packets with
crc/align error */
+ u32_t undersize; /* 1294->1297 packets < 64 bytes,
good crc */
+ u32_t oversize; /* 1298->129b packets > max_fl
bytes, good crc */
+ u32_t frag; /* 129c->129f packets < 64 bytes, bad
crc */
+ u32_t jab; /* 12a0->12a3 packets > max_fl bytes,
bad crc */
+ u32_t resvd_0; /* 12a4->12a7 */
+ u32_t p64; /* 12a8->12ab 64 byte packets */
+ u32_t p65to127; /* 12ac->12af 65 to 127 byte packets
*/
+ u32_t p128top255; /* 12b0->12b3 128 to 255 byte
packets */
+ u32_t p256to511; /* 12b4->12b7 256 to 511 byte
packets */
+ u32_t p512to1023; /* 12b8->12bb 512 to 1023 byte
packets */
+ u32_t p1024to2047; /* 12bc->12bf 1024 to 2047 byte
packets */
+ u32_t p_gte2048; /* 12c0->12c3 > 2048 byte packets
*/
+ u32_t octets; /* 12c4->12c7 octets */
+} fec_rmon_rstruct;
+
+typedef struct { /* fec, ieee receive */
+ u32_t drop; /* 12c8->12cb count of frames not
counted correctly */
+ u32_t frame_ok; /* 12cc->12cf frames received ok */
+ u32_t crc; /* 12d0->12d3 frames received with crc
error */
+ u32_t align; /* 12d4->12d7 frames received with
alignment error */
+ u32_t macerr; /* 12d8->12db receive fifo overflow
count */
+ u32_t fdxfc; /* 12dc->12df flow control pause
frames received */
+ u32_t octets_ok; /* 12e0->12e3 octet count for
frames received w/o error */
+} fec_ieee_rstruct;
+
+#define MCF5282_PUAPAR_URXD1 0x08 /* Port UA0 pin
configured for primary function (URXD1)*/
+#define MCF5282_PUAPAR_UTXD1 0x04 /* Port UA0 pin
configured for primary function (UTXD1)*/
+#define MCF5282_PUAPAR_URXD0 0x02 /* Port UA0 pin
configured for primary function (URXD0)*/
+#define MCF5282_PUAPAR_UTXD0 0x01 /* Port UA0 pin
configured for primary function (UTXD0)*/
+
+typedef struct { /* general purpose i/o */
+ u8_t porta; /* 100000 */
+ u8_t portb; /* 100001 */
+ u8_t portc; /* 100002 */
+ u8_t portd; /* 100003 */
+ u8_t porte; /* 100004 */
+ u8_t portf; /* 100005 */
+ u8_t portg; /* 100006 */
+ u8_t porth; /* 100007 */
+ u8_t portj; /* 100008 */
+ u8_t portdd; /* 100009 */
+ u8_t porteh; /* 10000a */
+ u8_t portel; /* 10000b */
+ u8_t portas; /* 10000c */
+ u8_t portqs; /* 10000d */
+ u8_t portsd; /* 10000e */
+ u8_t porttc; /* 10000f */
+ u8_t porttd; /* 100010 */
+ u8_t portua; /* 100011 */
+ u8_t pack00[2]; /* 100012->100013 */
+ u8_t ddra; /* 100014 */
+ u8_t ddrb; /* 100015 */
+ u8_t ddrc; /* 100016 */
+ u8_t ddrd; /* 100017 */
+ u8_t ddre; /* 100018 */
+ u8_t ddrf; /* 100019 */
+ u8_t ddrg; /* 10001a */
+ u8_t ddrh; /* 10001b */
+ u8_t ddrj; /* 10001c */
+ u8_t ddrdd; /* 10001d */
+ u8_t ddreh; /* 10001e */
+ u8_t ddrel; /* 10001f */
+ u8_t ddras; /* 100020 */
+ u8_t ddrqs; /* 100021 */
+ u8_t ddrsd; /* 100022 */
+ u8_t ddrtc; /* 100023 */
+ u8_t ddrtd; /* 100024 */
+ u8_t ddrua; /* 100025 */
+ u8_t pack01[2]; /* 100026->100027 */
+ u8_t portap; /* 100028 */
+ u8_t portbp; /* 100029 */
+ u8_t portcp; /* 10002a */
+ u8_t portdp; /* 10002b */
+ u8_t portep; /* 10002c */
+ u8_t portfp; /* 10002d */
+ u8_t portgp; /* 10002e */
+ u8_t porthp; /* 10002f */
+ u8_t portjp; /* 100030 */
+ u8_t portddp; /* 100031 */
+ u8_t portehp; /* 100032 */
+ u8_t portelp; /* 100033 */
+ u8_t portasp; /* 100034 */
+ u8_t portqsp; /* 100035 */
+ u8_t portsdp; /* 100036 */
+ u8_t porttcp; /* 100037 */
+ u8_t porttdp; /* 100038 */
+ u8_t portuap; /* 100039 */
+ u8_t pack02[2]; /* 10003a->10003b */
+ u8_t clra; /* 10003c */
+ u8_t clrb; /* 10003d */
+ u8_t clrc; /* 10003e */
+ u8_t clrd; /* 10003f */
+ u8_t clre; /* 100040 */
+ u8_t clrf; /* 100041 */
+ u8_t clrg; /* 100042 */
+ u8_t clrh; /* 100043 */
+ u8_t clrj; /* 100044 */
+ u8_t clrdd; /* 100045 */
+ u8_t clreh; /* 100046 */
+ u8_t clrel; /* 100047 */
+ u8_t clras; /* 100048 */
+ u8_t clrqs; /* 100049 */
+ u8_t clrsd; /* 10004a */
+ u8_t clrtc; /* 10004b */
+ u8_t clrtd; /* 10004c */
+ u8_t clrua; /* 10004d */
+ u8_t pack03[2]; /* 10004e->10004f */
+ u8_t pbcdpar; /* 100050 */
+ u8_t pfpar; /* 100051 */
+ u16_t pepar; /* 100052-100053 */
+ u8_t pjpar; /* 100054 */
+ u8_t psdpar; /* 100055 */
+ u16_t paspar; /* 100056->100057 */
+ u8_t pehlpar; /* 100058 */
+ u8_t pqspar; /* 100059 */
+ u8_t ptcpar; /* 10005a */
+ u8_t ptdpar; /* 10005b */
+ u8_t puapar; /* 10005c */
+ u8_t pack04[3]; /* 10005d->10005f*/
+} gpiostruct;
+
+typedef struct { /* reset controller module */
+
+ u8_t rcr; /* 110000->110000 reset control register
*/
+ u8_t rsr; /* 110001->110001 reset status register
*/
+
+
+} resetstruct;
+
+typedef struct { /* chip configuration module */
+
+ u16_t ccr; /* 110004->110005 chip configuration
register */
+ u8_t pack00; /* 110006 */
+ u8_t lpcr; /* 110007 low power control register */
+ u16_t rcon; /* 110008->110009 reset configuration
register*/
+ u16_t cir; /* 11000a->11000b chip identification
register*/
+
+
+} ccmstruct;
+
+#define MCF5282_CLOCK_SYNCR_LOLRE 0x8000
+#define MCF5282_CLOCK_SYNCR_MFD2 0x4000
+#define MCF5282_CLOCK_SYNCR_MFD1 0x2000
+#define MCF5282_CLOCK_SYNCR_MFD0 0x1000
+#define MCF5282_CLOCK_SYNCR_LOCRE 0x0800
+#define MCF5282_CLOCK_SYNCR_RDF2 0x0400
+#define MCF5282_CLOCK_SYNCR_RDF1 0x0200
+#define MCF5282_CLOCK_SYNCR_RFD0 0x0100
+#define MCF5282_CLOCK_SYNCR_LOCEN 0x0080
+#define MCF5282_CLOCK_SYNCR_DISCLK 0x0040
+#define MCF5282_CLOCK_SYNCR_FWKUP 0x0020
+#define MCF5282_CLOCK_SYNCR_STPMD1 0x0008
+#define MCF5282_CLOCK_SYNCR_STPMD0 0x0004
+
+#define MCF5282_CLOCK_SYNSR_PLLMODE 0x80
+#define MCF5282_CLOCK_SYNSR_PLLSEL 0x40
+#define MCF5282_CLOCK_SYNSR_PLLREF 0x20
+#define MCF5282_CLOCK_SYNSR_LOCKS 0x10
+#define MCF5282_CLOCK_SYNSR_LOCK 0x08
+#define MCF5282_CLOCK_SYNSR_LOCS 0x04
+
+
+typedef struct
+{ /* clock module */
+ u16_t syncr; /* 120000->120001 synthesizer control
register */
+ u8_t synsr; /* 120002->120002 synthesizer
status register */
+
+} clockstruct;
+
+
+typedef struct { /* edge port module */
+
+ u16_t eppar; /* 130000->130001 eport pin assignment
register */
+ u8_t epddr; /* 130002->130002 eport data direction
register */
+ u8_t epier; /* 130003->130003 eport interrupt
enable register */
+ u8_t epdr; /* 130004->130004 eport data register */
+ u8_t eppdr; /* 130005->130005 eport pin data
register */
+ u8_t epfr; /* 130006->130006 eport flag register */
+
+
+} eportstruct;
+
+typedef struct /* watchdog timer module */
+{
+ u16_t wcr; /* 140000->140001 watchdog control
register */
+ u16_t wmr; /* 140002->140003 watchdog modulus
register */
+ u16_t wcntr; /* 140004->140005 watchdog count
register */
+ u16_t wsr; /* 140006->140007 watchdog service
register */
+} wtmstruct;
+
+#define MCF5282_PIT_PCSR_PRE_DIV_65535 0x0F00
+#define MCF5282_PIT_PCSR_PRE_DIV_32768 0x0E00
+#define MCF5282_PIT_PCSR_PRE_DIV_16384 0x0D00
+#define MCF5282_PIT_PCSR_PRE_DIV_8192 0x0C00
+#define MCF5282_PIT_PCSR_PRE_DIV_4096 0x0B00
+#define MCF5282_PIT_PCSR_PRE_DIV_2048 0x0A00
+#define MCF5282_PIT_PCSR_PRE_DIV_1024 0x0900
+#define MCF5282_PIT_PCSR_PRE_DIV_512 0x0800
+#define MCF5282_PIT_PCSR_PRE_DIV_256 0x0700
+#define MCF5282_PIT_PCSR_PRE_DIV_128 0x0600
+#define MCF5282_PIT_PCSR_PRE_DIV_64 0x0500
+#define MCF5282_PIT_PCSR_PRE_DIV_32 0x0400
+#define MCF5282_PIT_PCSR_PRE_DIV_16 0x0300
+#define MCF5282_PIT_PCSR_PRE_DIV_8 0x0200
+#define MCF5282_PIT_PCSR_PRE_DIV_4 0x0100
+#define MCF5282_PIT_PCSR_PRE_DIV_2 0x0000
+#define MCF5282_PIT_PCSR_DOZE 0x0040
+#define MCF5282_PIT_PCSR_HALTED 0x0020
+#define MCF5282_PIT_PCSR_OVW 0x0010
+#define MCF5282_PIT_PCSR_PIE 0x0008
+#define MCF5282_PIT_PCSR_PIF 0x0004
+#define MCF5282_PIT_PCSR_RLD 0x0002
+#define MCF5282_PIT_PCSR_EN 0x0001
+
+typedef struct /* programmable interrupt timer
modules */
+{
+ u16_t pcsr; /* 16bit control and status register
*/
+ u16_t pmr; /* 16bit modulus register */
+ u16_t pcntr; /* 16bit count register */
+ u8_t pack00[65530]; /* 0xfffc */
+} pitstruct;
+
+typedef struct { /* queued analog-to-digital
converter module */
+
+ u16_t qadcmcr; /* 190000->190001 qadc module
configuration register */
+ u8_t pack00[4]; /* 190002->190005 */
+ u8_t portqa; /* 190006->190006 (qa) port data
register */
+ u8_t portqb; /* 190007->190007 (qb) port data
register */
+ u8_t ddrqa; /* 190008->190008 port qa data
direction register */
+ u8_t ddrqb; /* 190009->190009 port qb data
direction register */
+ u16_t qacr0; /* 19000a->19000b qadc control
register 0 */
+ u16_t qacr1; /* 19000c->19000d qadc control
register 1 */
+ u16_t qacr2; /* 19000e->19000f qadc control
register 2 */
+ u16_t qasr0; /* 190010->190011 qadc status
register 0 */
+ u16_t qasr1; /* 190012->190013 qadc status
register 1 */
+ u8_t pack01[491]; /* 190014->1901ff */
+ u16_t ccw[64]; /* 190200->190201 conversion command
word table */
+ u16_t rjurr[64]; /* 190280->190281 right-justified
unsigned result register */
+ u16_t ljsrr[64]; /* 190300->190301 left-justified
signed result register */
+ u16_t ljurr[64]; /* 190380->190381 left-justified
unsigned result register */
+
+
+} qadcstruct;
+
+typedef struct { /* general purpose timer modules */
+ u8_t ios; /* 8bit ic/oc select register */
+ u8_t cforc; /* 8bit compare force register */
+ u8_t oc3m; /* 8bit output compare 3 mask register
*/
+ u8_t oc3d; /* 8bit output compare 3 data register
*/
+ u16_t cnt; /* 16bit counter register */
+ u8_t scr1; /* 8bit system control register 1 */
+ u8_t pack00; /* 8bit reserved */
+ u8_t tov; /* 8bit toggle on overflow register */
+ u8_t ctl1; /* 8bit control register 1 */
+ u8_t pack01; /* 8bit reserved */
+ u8_t ctl2; /* 8bit control register 2 */
+ u8_t tie; /* 8bit interupt enable register */
+ u8_t scr2; /* 8bit system control register 2 */
+
+#define MCF5282_GPT_SCR2_PRESCALE_DIV_1 0x00
+#define MCF5282_GPT_SCR2_PRESCALE_DIV_2 0x01
+#define MCF5282_GPT_SCR2_PRESCALE_DIV_4 0x02
+#define MCF5282_GPT_SCR2_PRESCALE_DIV_8 0x03
+#define MCF5282_GPT_SCR2_PRESCALE_DIV_16 0x04
+#define MCF5282_GPT_SCR2_PRESCALE_DIV_32 0x05
+#define MCF5282_GPT_SCR2_PRESCALE_DIV_64 0x06
+#define MCF5282_GPT_SCR2_PRESCALE_DIV_128 0x07
+
+ u8_t flg1; /* 8bit flag register 1 */
+ u8_t flg2; /* 8bit flag register 2 */
+ u16_t c0; /* 16bit channel 0 */
+ u16_t c1; /* 16bit channel 1 */
+ u16_t c2; /* 16bit channel 2 */
+ u16_t c3; /* 16bit channel 3 */
+ u8_t pactl; /* 8bit pulse accumulator control
register */
+ u8_t paflg; /* 8bit pulse accumulator flag register
*/
+ u16_t pacnt; /* 16bit pulse accumulator counter
register */
+ u8_t pack02; /* 8bit reserved */
+ u8_t port; /* 8bit port data register */
+ u8_t ddr; /* 8bit data direction register */
+ u8_t pack03[65504]; /* 0xffe2 */
+} gptstruct;
+
+typedef struct {
+ u8_t bTimeStamp;
+ u8_t bStatus;
+ u16_t id_hi;
+ u16_t id_low;
+ u8_t data[8];
+ u16_t reserved;
+} can_mb_struct;
+
+typedef struct { /* flexcan module */
+
+ u16_t canmcr; /* 1c0000->1c0001 can module
configuration register */
+ u8_t pack00[4]; /* 1c0002->1c0005 */
+ u8_t canctrl0; /* 1c0006->1c0006 flexcan control
register 0 */
+ u8_t canctrl1; /* 1c0007->1c0007 flexcan control
register 1 */
+ u8_t presdiv; /* 1c0008->1c0008 prescaler divide
register */
+ u8_t canctrl2; /* 1c0009->1c0009 flexcan control
register 2 */
+ u16_t timer; /* 1c000a->1c000b free running timer
*/
+ u8_t pack01[4]; /* 1c000c->1c000f */
+ u32_t rxgmask; /* 1c0010->1c0013 receive global
mask register */
+ u32_t rx14mask; /* 1c0014->1c0017 receive mask
register */
+ u32_t rx15mask; /* 1c0018->1c001b receive mask
register */
+ u8_t pack02[4]; /* 1c001c->1c001f */
+ u16_t esr; /* 1c0020->1c0021 flexcan error and
status register */
+ u16_t imask; /* 1c0022->1c0023 interrupt mask
register */
+ u16_t iflag; /* 1c0024->1c0025 interrupt flag
register */
+ u8_t rxerrcnt; /* 1c0026->1c0026 flexcan receive
error counter */
+ u8_t txerrcnt; /* 1c0027->1c0027 flexcan transmit
error counter */
+ u8_t pack03[88]; /* 1c0034->1c007f */
+ can_mb_struct mbs[16]; /*1c_0080 -> 1c_017F */
+
+} flexcanstruct;
+
+typedef struct { /* coldfire flash module */
+
+ u16_t cfmmcr; /* 1d0000->1d0001 cfm
configuration register */
+ u8_t cfmclkd; /* 1d0002->1d0002 cfm clock
divider register */
+ u8_t pack00[5]; /* 1d0003->1d0007 */
+ u32_t cfmsec; /* 1d0008->1d000b cfm security
register */
+ u8_t pack01[4]; /* 1d000c->1d000f */
+ u32_t cfmprot; /* 1d0010->1d0013 cfm protection
register */
+ u32_t cfmsacc; /* 1d0014->1d0017 cfm supervisor
access register */
+ u32_t cfmdacc; /* 1d0018->1d001b cfm data access
register */
+ u8_t pack02[4]; /* 1d001c->1d001f */
+ u8_t cfmusat; /* 1d0020->1d0020 cfm user status
register */
+ u8_t pack03[3]; /* 1d0021->1d0023 */
+ u8_t cfmcmd; /* 1d0024->1d0024 cfm command
register */
+ u8_t pack04[28]; /* 1d0025->1d0041 */
+ u16_t cfmdisu; /* 1d0042->1d0044 */
+} cfmstruct;
+
+/* ---------------------- 5282 main struct
------------------------- */
+typedef struct
+{
+ scmstruct scm; /* 0x000000->0x00003f - System
Control Module*/
+
+ sdramcstruct sdram; /* 0x000040->0x000057 */
+
+ u8_t pack00[40]; /* 0x000058->0x00007f */
+
+ csstruct cs[8]; /* 0x000080->0x0000df */
+
+ u8_t pack01[32]; /* 0x0000e0->0x0000ff */
+
+ dmastruct dma[4]; /* 0x000100->0x0001ff */
+
+ uartstruct uart[3]; /* 0x000200->0x0002bc */
+
+ u8_t pack03[64]; /* 0x0002bd->0x0002ff */
+
+ i2cstruct i2c; /* 0x000300->0x000313 */
+
+ u8_t pack04[44]; /* 0x000314->0x00033f */
+
+ qspistruct qspi; /* 0x000340->0x000357 */
+
+ u8_t pack05[168]; /* 0x000358->0x0003ff */
+
+ dmatimerstruct timer[4]; /* 0x000400->0x00050f */
+
+ u8_t pack06[1792]; /* 0x000510->0x000bff */
+
+ intcstruct intc[2];
+
+ u8_t pack07[480]; /* 0x000e00->0x000fdf */
+
+ giacstruct giac; /* 0x000fe0->0x000fff */
+
+ u8_t pack08[4]; /* 0x001000->0x001003 */
+
+ fecstruct fec; /* 0x001004->0x00118b */
+
+ u8_t pack09[116]; /* 0x00118c->0x0011ff */
+
+ fec_rmon_tstruct fec_rmon_t; /* 0x001200->0x001247
*/
+
+ fec_ieee_tstruct fec_ieee_t; /* 0x001248->0x001277
*/
+
+ u8_t pack10[12]; /* 0x001278->0x001283 */
+
+ fec_rmon_rstruct fec_rmon_r; /* 0x001284->0x0012c7
*/
+
+ fec_ieee_rstruct fec_ieee_r; /* 0x0012c8->0x0012e3
*/
+
+ u8_t pack11[1043740]; /* 0x0012e4->0x0fffff */
+
+ gpiostruct gpio; /* 0x100000->0x10005c */
+
+ u8_t pack12[0xFF9F]; /* 0x100060->0x10ffff */
+
+ resetstruct reset; /* 0x110000->0x110001 */
+
+ u8_t pack13[2]; /* 0x110002->0x110003 */
+
+ ccmstruct ccm; /* 0x110004->0x11000b */
+
+ u8_t pack14[65524]; /* 0x11000c->0x11ffff */
+
+ clockstruct clock; /* 0x120000->0x120001 */
+
+ u8_t pack15[65532]; /* 0x120002->0x12ffff */
+
+ eportstruct eport; /* 0x130000->0x130006 */
+
+ u8_t pack16[65527]; /* 0x130007->0x13ffff */
+
+ wtmstruct wtm; /* 0x140000->0x140007 */
+
+ u8_t pack17[65528]; /* 0x140008->0x14ffff */
+
+ pitstruct pit[4]; /* 0x150000->0x18ffff */
+
+ qadcstruct qadc; /* 0x190000->0x1903FF */
+
+ u8_t pack18[64512]; /* 0x190400->0x19ffff */
+
+ gptstruct gpt[2]; /* 0x1a0000->0x19bfff */
+
+ flexcanstruct flexcan; /* 0x1c0000->0x1c017F */
+
+ u8_t pack19[65152]; /* 0x1c0200->0x1cffff */
+
+ cfmstruct cfm; /* 0x1d0000->0x1d0044 */
+
+
+ } mcf5282_sim_t;
+
+#endif /* MCF5282_SIM_H */
+
Index:
packages/hal/m68k/mcf52xx/mcf5282/proc/current/include/proc_arch.h
===================================================================
RCS file:
packages/hal/m68k/mcf52xx/mcf5282/proc/current/include/proc_arch.h
diff -N
packages/hal/m68k/mcf52xx/mcf5282/proc/current/include/proc_arch.h
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++
packages/hal/m68k/mcf52xx/mcf5282/proc/current/include/proc_arch.h
1 Jan 1970 00:00:00 -0000
@@ -0,0 +1,65 @@
+#ifndef CYGONCE_HAL_PROC_ARCH_H
+#define CYGONCE_HAL_PROC_ARCH_H
+//=============================================================================
+//
+// proc_arch.h
+//
+// Processor variant specific abstractions
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded
Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red
Hat, Inc.
+//
+// eCos is free software; you can redistribute it
and/or modify it under
+// the terms of the GNU General Public License as
published by the Free
+// Software Foundation; either version 2 or (at your
option) any later version.
+//
+// eCos is distributed in the hope that it will be
useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of
MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU
General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General
Public License along
+// with eCos; if not, write to the Free Software
Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307
USA.
+//
+// As a special exception, if other files instantiate
templates or use macros
+// or inline functions from this file, or you compile
this file and link it
+// with other works to produce a work based on this
file, this file does not
+// by itself cause the resulting work to be covered
by the GNU General Public
+// License. However the source code for this file
must still be made available
+// in accordance with section (3) of the GNU General
Public License.
+//
+// This exception does not invalidate any other
reasons why a work based on
+// this file might be covered by the GNU General
Public License.
+//
+// Alternative licenses for eCos may be arranged by
contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//=============================================================================
+
+#include <pkgconf/hal.h>
+#include <cyg/infra/cyg_type.h>
+
+#include <cyg/hal/mcf5282_sim.h>
+//#include <cyg/hal/hal_memmap.h>
+
+// Declare the global pointer to the SIM registers.
+// Everyone should use the MCF5282_SIM macro so it
can be easily changed.
+externC volatile mcf5282_sim_t * const mcf5282_sim_p;
+#define MCF5282_SIM mcf5282_sim_p
+
+/*
************************************************************************
*/
+/* These routines write to the special purpose
registers in the ColdFire */
+/* core. Since these registers are write-only in the
supervisor model, no */
+/* corresponding read routines exist.
*/
+
+externC void mcf5282_wr_mbar(CYG_WORD32);
+externC void mcf5282_wr_vbr(CYG_WORD32);
+
+//-----------------------------------------------------------------------------
+#endif // CYGONCE_HAL_PROC_ARCH_H
+
Index:
packages/hal/m68k/mcf52xx/mcf5282/proc/current/include/proc_intr.h
===================================================================
RCS file:
packages/hal/m68k/mcf52xx/mcf5282/proc/current/include/proc_intr.h
diff -N
packages/hal/m68k/mcf52xx/mcf5282/proc/current/include/proc_intr.h
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++
packages/hal/m68k/mcf52xx/mcf5282/proc/current/include/proc_intr.h
1 Jan 1970 00:00:00 -0000
@@ -0,0 +1,124 @@
+#ifndef CYGONCE_HAL_PROC_INTR_H
+#define CYGONCE_HAL_PROC_INTR_H
+
+//==========================================================================
+//
+// proc_intr.h
+//
+// mcf5282 Processor variant interrupt and clock
support
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded
Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red
Hat, Inc.
+//
+// eCos is free software; you can redistribute it
and/or modify it under
+// the terms of the GNU General Public License as
published by the Free
+// Software Foundation; either version 2 or (at your
option) any later version.
+//
+// eCos is distributed in the hope that it will be
useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of
MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU
General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General
Public License along
+// with eCos; if not, write to the Free Software
Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307
USA.
+//
+// As a special exception, if other files instantiate
templates or use macros
+// or inline functions from this file, or you compile
this file and link it
+// with other works to produce a work based on this
file, this file does not
+// by itself cause the resulting work to be covered
by the GNU General Public
+// License. However the source code for this file
must still be made available
+// in accordance with section (3) of the GNU General
Public License.
+//
+// This exception does not invalidate any other
reasons why a work based on
+// this file might be covered by the GNU General
Public License.
+//
+// Alternative licenses for eCos may be arranged by
contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+
+#include <pkgconf/hal.h>
+#include <cyg/infra/cyg_type.h>
+
+// Include any platform specific interrupt
definitions.
+#include <cyg/hal/plf_intr.h>
+
+// Include for the SIM address (MCF5282_SIM).
+#include <cyg/hal/proc_arch.h>
+
+//---------------------------------------------------------------------------
+// Interrupt controller management
+
+// This chip has a programmable interrupt vector
base which is different
+// from the vector base register (VBR). All
interrupts from the interrupt
+// controller are offsets from the programmable
interrupt vector register
+// (PIVR).
+
+#define HAL_PROG_INTC0_VEC_BASE 64 // offset for
interrupt controller 0
+#define HAL_PROG_INTC1_VEC_BASE 128 // offset for
interrupt controller 1
+
+// Vector numbers defined by the interrupt
controller.
+// These are all relative to the interrupt vector
base number.
+#define CYGNUM_HAL_VECTOR_EPORT_EPF1 (1 +
HAL_PROG_INTC0_VEC_BASE)
+#define CYGNUM_HAL_VECTOR_EPORT_EPF2 (2 +
HAL_PROG_INTC0_VEC_BASE)
+#define CYGNUM_HAL_VECTOR_EPORT_EPF3 (3 +
HAL_PROG_INTC0_VEC_BASE)
+#define CYGNUM_HAL_VECTOR_EPORT_EPF4 (4 +
HAL_PROG_INTC0_VEC_BASE)
+#define CYGNUM_HAL_VECTOR_EPORT_EPF5 (5 +
HAL_PROG_INTC0_VEC_BASE)
+#define CYGNUM_HAL_VECTOR_EPORT_EPF6 (6 +
HAL_PROG_INTC0_VEC_BASE)
+#define CYGNUM_HAL_VECTOR_EPORT_EPF7 (7 +
HAL_PROG_INTC0_VEC_BASE)
+#define CYGNUM_HAL_VECTOR_SCM (8 +
HAL_PROG_INTC0_VEC_BASE)
+#define CYGNUM_HAL_VECTOR_DMA_CHAN1 (9 +
HAL_PROG_INTC0_VEC_BASE)
+#define CYGNUM_HAL_VECTOR_DMA_CHAN2 (10 +
HAL_PROG_INTC0_VEC_BASE)
+#define CYGNUM_HAL_VECTOR_DMA_CHAN3 (11 +
HAL_PROG_INTC0_VEC_BASE)
+#define CYGNUM_HAL_VECTOR_DMA_CHAN4 (12 +
HAL_PROG_INTC0_VEC_BASE)
+#define CYGNUM_HAL_VECTOR_UART0 (13 +
HAL_PROG_INTC0_VEC_BASE)
+#define CYGNUM_HAL_VECTOR_UART1 (14 +
HAL_PROG_INTC0_VEC_BASE)
+#define CYGNUM_HAL_VECTOR_UART2 (15 +
HAL_PROG_INTC0_VEC_BASE)
+
+#define CYGNUM_HAL_VECTOR_FEC_X_INTF (23 +
HAL_PROG_INTC0_VEC_BASE)
+#define CYGNUM_HAL_VECTOR_FEC_X_INTB (24 +
HAL_PROG_INTC0_VEC_BASE)
+#define CYGNUM_HAL_VECTOR_FEC_UN (25 +
HAL_PROG_INTC0_VEC_BASE)
+#define CYGNUM_HAL_VECTOR_FEC_RL (26 +
HAL_PROG_INTC0_VEC_BASE)
+#define CYGNUM_HAL_VECTOR_FEC_R_INTF (27 +
HAL_PROG_INTC0_VEC_BASE)
+#define CYGNUM_HAL_VECTOR_FEC_R_INTB (28 +
HAL_PROG_INTC0_VEC_BASE)
+#define CYGNUM_HAL_VECTOR_FEC_MII (29 +
HAL_PROG_INTC0_VEC_BASE)
+#define CYGNUM_HAL_VECTOR_FEC_LC (30 +
HAL_PROG_INTC0_VEC_BASE)
+#define CYGNUM_HAL_VECTOR_FEC_HBERR (31 +
HAL_PROG_INTC0_VEC_BASE)
+#define CYGNUM_HAL_VECTOR_FEC_GRA (32 +
HAL_PROG_INTC0_VEC_BASE)
+#define CYGNUM_HAL_VECTOR_FEC_EBERR (33 +
HAL_PROG_INTC0_VEC_BASE)
+#define CYGNUM_HAL_VECTOR_FEC_BABT (34 +
HAL_PROG_INTC0_VEC_BASE)
+#define CYGNUM_HAL_VECTOR_FEC_BABR (35 +
HAL_PROG_INTC0_VEC_BASE)
+
+#define CYGNUM_HAL_VECTOR_PIT0 (55 +
HAL_PROG_INTC0_VEC_BASE)
+#define CYGNUM_HAL_VECTOR_PIT1 (56 +
HAL_PROG_INTC0_VEC_BASE)
+#define CYGNUM_HAL_VECTOR_PIT2 (57 +
HAL_PROG_INTC0_VEC_BASE)
+#define CYGNUM_HAL_VECTOR_PIT3 (58 +
HAL_PROG_INTC0_VEC_BASE)
+
+//---------------------------------------------------------------------------
+// Interrupt controller macros.
+
+externC void hal_interrupt_mask(int);
+externC void hal_interrupt_unmask(int);
+externC void hal_interrupt_acknowledge(int);
+externC void hal_interrupt_configure(int, int, int);
+externC void hal_interrupt_set_level(int, int);
+
+#define HAL_INTERRUPT_MASK( _vector_ )
\
+ hal_interrupt_mask( _vector_ )
+#define HAL_INTERRUPT_UNMASK( _vector_ )
\
+ hal_interrupt_unmask( _vector_ )
+#define HAL_INTERRUPT_ACKNOWLEDGE( _vector_ )
\
+ hal_interrupt_acknowledge( _vector_ )
+#define HAL_INTERRUPT_CONFIGURE( _vector_, _level_,
_up_ ) \
+ hal_interrupt_configure( _vector_, _level_, _up_
)
+#define HAL_INTERRUPT_SET_LEVEL( _vector_, _level_ )
\
+ hal_interrupt_set_level( _vector_, _level_ )
+
+//--------------------------------------------------------------------------
+#endif // ifndef CYGONCE_HAL_PROC_INTR_H
+
Index:
packages/hal/m68k/mcf52xx/mcf5282/proc/current/include/proc_startup.h
===================================================================
RCS file:
packages/hal/m68k/mcf52xx/mcf5282/proc/current/include/proc_startup.h
diff -N
packages/hal/m68k/mcf52xx/mcf5282/proc/current/include/proc_startup.h
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++
packages/hal/m68k/mcf52xx/mcf5282/proc/current/include/proc_startup.h
1 Jan 1970 00:00:00 -0000
@@ -0,0 +1,49 @@
+#ifndef _PROC_STARTUP_H
+#define _PROC_STARTUP_H
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded
Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red
Hat, Inc.
+//
+// eCos is free software; you can redistribute it
and/or modify it under
+// the terms of the GNU General Public License as
published by the Free
+// Software Foundation; either version 2 or (at your
option) any later version.
+//
+// eCos is distributed in the hope that it will be
useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of
MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU
General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General
Public License along
+// with eCos; if not, write to the Free Software
Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307
USA.
+//
+// As a special exception, if other files instantiate
templates or use macros
+// or inline functions from this file, or you compile
this file and link it
+// with other works to produce a work based on this
file, this file does not
+// by itself cause the resulting work to be covered
by the GNU General Public
+// License. However the source code for this file
must still be made available
+// in accordance with section (3) of the GNU General
Public License.
+//
+// This exception does not invalidate any other
reasons why a work based on
+// this file might be covered by the GNU General
Public License.
+//
+// Alternative licenses for eCos may be arranged by
contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+
+#include <cyg/infra/cyg_type.h>
+
+// Include the platform-specific startup header.
+
+#include <cyg/hal/plf_startup.h>
+
+// Processor-specific reset vector
initialization routine
+
+externC void proc_reset(void);
+
+#endif // _PROC_STARTUP_H
+
Index:
packages/hal/m68k/mcf52xx/mcf5282/proc/current/src/memcpy.c
===================================================================
RCS file:
packages/hal/m68k/mcf52xx/mcf5282/proc/current/src/memcpy.c
diff -N
packages/hal/m68k/mcf52xx/mcf5282/proc/current/src/memcpy.c
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++
packages/hal/m68k/mcf52xx/mcf5282/proc/current/src/memcpy.c
1 Jan 1970 00:00:00 -0000
@@ -0,0 +1,123 @@
+//==========================================================================
+//
+// memcpy.c
+//
+// memcpy() routine for coldfire
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded
Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red
Hat, Inc.
+//
+// eCos is free software; you can redistribute it
and/or modify it under
+// the terms of the GNU General Public License as
published by the Free
+// Software Foundation; either version 2 or (at your
option) any later version.
+//
+// eCos is distributed in the hope that it will be
useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of
MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU
General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General
Public License along
+// with eCos; if not, write to the Free Software
Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307
USA.
+//
+// As a special exception, if other files instantiate
templates or use macros
+// or inline functions from this file, or you compile
this file and link it
+// with other works to produce a work based on this
file, this file does not
+// by itself cause the resulting work to be covered
by the GNU General Public
+// License. However the source code for this file
must still be made available
+// in accordance with section (3) of the GNU General
Public License.
+//
+// This exception does not invalidate any other
reasons why a work based on
+// this file might be covered by the GNU General
Public License.
+//
+// Alternative licenses for eCos may be arranged by
contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+
+/* INCLUDES */
+
+#include <cyg/infra/cyg_type.h> /* Common type
definitions */
+#include <stddef.h> /* Compiler defns
such as size_t, NULL etc. */
+
+/* EXPORTED SYMBOLS */
+
+externC void *
+memcpy( void * s1, const void * s2, size_t n )
__attribute__((alias("_memcpy")));
+
+/* FUNCTIONS */
+
+void *
+_memcpy( void * s1, const void * s2, size_t n )
+{
+ char * dst = (char *) s1;
+ const char * src = (const char *) s2;
+ long longwords;
+ int_t rem_bytes;
+ int_t loops;
+ int_t loop_index;
+
+ /* Don't worry about alignment on the
coldfire. Most large */
+ /* structures should be aligned anyway.
*/
+
+ longwords = (long)(n / 4);
+ rem_bytes = n % 4;
+ loops = (int_t)(longwords / 32);
+ loop_index = (int_t)(longwords % 32);
+
+ switch (loop_index)
+ {
+ do
+ {
+ *((cyg_uint32*)dst)++ =
*((cyg_uint32*)src)++;
+ case 31: *((cyg_uint32*)dst)++ =
*((cyg_uint32*)src)++;
+ case 30: *((cyg_uint32*)dst)++ =
*((cyg_uint32*)src)++;
+ case 29: *((cyg_uint32*)dst)++ =
*((cyg_uint32*)src)++;
+ case 28: *((cyg_uint32*)dst)++ =
*((cyg_uint32*)src)++;
+ case 27: *((cyg_uint32*)dst)++ =
*((cyg_uint32*)src)++;
+ case 26: *((cyg_uint32*)dst)++ =
*((cyg_uint32*)src)++;
+ case 25: *((cyg_uint32*)dst)++ =
*((cyg_uint32*)src)++;
+ case 24: *((cyg_uint32*)dst)++ =
*((cyg_uint32*)src)++;
+ case 23: *((cyg_uint32*)dst)++ =
*((cyg_uint32*)src)++;
+ case 22: *((cyg_uint32*)dst)++ =
*((cyg_uint32*)src)++;
+ case 21: *((cyg_uint32*)dst)++ =
*((cyg_uint32*)src)++;
+ case 20: *((cyg_uint32*)dst)++ =
*((cyg_uint32*)src)++;
+ case 19: *((cyg_uint32*)dst)++ =
*((cyg_uint32*)src)++;
+ case 18: *((cyg_uint32*)dst)++ =
*((cyg_uint32*)src)++;
+ case 17: *((cyg_uint32*)dst)++ =
*((cyg_uint32*)src)++;
+ case 16: *((cyg_uint32*)dst)++ =
*((cyg_uint32*)src)++;
+ case 15: *((cyg_uint32*)dst)++ =
*((cyg_uint32*)src)++;
+ case 14: *((cyg_uint32*)dst)++ =
*((cyg_uint32*)src)++;
+ case 13: *((cyg_uint32*)dst)++ =
*((cyg_uint32*)src)++;
+ case 12: *((cyg_uint32*)dst)++ =
*((cyg_uint32*)src)++;
+ case 11: *((cyg_uint32*)dst)++ =
*((cyg_uint32*)src)++;
+ case 10: *((cyg_uint32*)dst)++ =
*((cyg_uint32*)src)++;
+ case 9: *((cyg_uint32*)dst)++ =
*((cyg_uint32*)src)++;
+ case 8: *((cyg_uint32*)dst)++ =
*((cyg_uint32*)src)++;
+ case 7: *((cyg_uint32*)dst)++ =
*((cyg_uint32*)src)++;
+ case 6: *((cyg_uint32*)dst)++ =
*((cyg_uint32*)src)++;
+ case 5: *((cyg_uint32*)dst)++ =
*((cyg_uint32*)src)++;
+ case 4: *((cyg_uint32*)dst)++ =
*((cyg_uint32*)src)++;
+ case 3: *((cyg_uint32*)dst)++ =
*((cyg_uint32*)src)++;
+ case 2: *((cyg_uint32*)dst)++ =
*((cyg_uint32*)src)++;
+ case 1: *((cyg_uint32*)dst)++ =
*((cyg_uint32*)src)++;
+ case 0: ; /* Keep compiler from
complaining. */
+ } while (--loops >= 0);
+ }
+
+ /* Clean up the remaining bytes. */
+
+ while (--rem_bytes >= 0)
+ {
+ *dst++ = *src++;
+ }
+
+ return s1;
+
+} /* _memcpy() */
+
+/* EOF memcpy.c */
Index:
packages/hal/m68k/mcf52xx/mcf5282/proc/current/src/proc_arch.S
===================================================================
RCS file:
packages/hal/m68k/mcf52xx/mcf5282/proc/current/src/proc_arch.S
diff -N
packages/hal/m68k/mcf52xx/mcf5282/proc/current/src/proc_arch.S
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++
packages/hal/m68k/mcf52xx/mcf5282/proc/current/src/proc_arch.S
1 Jan 1970 00:00:00 -0000
@@ -0,0 +1,68 @@
+##=============================================================================
+##
+## proc_arch.S
+##
+## mcf5282 processor code
+##
+##=============================================================================
+##=============================================================================
+#####ECOSGPLCOPYRIGHTBEGIN####
+## -------------------------------------------
+## This file is part of eCos, the Embedded
Configurable Operating System.
+## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red
Hat, Inc.
+##
+## eCos is free software; you can redistribute it
and/or modify it under
+## the terms of the GNU General Public License as
published by the Free
+## Software Foundation; either version 2 or (at your
option) any later version.
+##
+## eCos is distributed in the hope that it will be
useful, but WITHOUT ANY
+## WARRANTY; without even the implied warranty of
MERCHANTABILITY or
+## FITNESS FOR A PARTICULAR PURPOSE. See the GNU
General Public License
+## for more details.
+##
+## You should have received a copy of the GNU General
Public License along
+## with eCos; if not, write to the Free Software
Foundation, Inc.,
+## 59 Temple Place, Suite 330, Boston, MA 02111-1307
USA.
+##
+## As a special exception, if other files instantiate
templates or use macros
+## or inline functions from this file, or you compile
this file and link it
+## with other works to produce a work based on this
file, this file does not
+## by itself cause the resulting work to be covered
by the GNU General Public
+## License. However the source code for this file
must still be made available
+## in accordance with section (3) of the GNU General
Public License.
+##
+## This exception does not invalidate any other
reasons why a work based on
+## this file might be covered by the GNU General
Public License.
+##
+## Alternative licenses for eCos may be arranged by
contacting Red Hat, Inc.
+## at http://sources.redhat.com/ecos/ecos-license/
+## -------------------------------------------
+#####ECOSGPLCOPYRIGHTEND####
+##=============================================================================
+
+#include <pkgconf/hal.h>
+
+#------------------------------------------------------------------------------
+# function declaration macro
+
+#define FUNC_START(name) \
+ .text; \
+ .even; \
+ .globl name; \
+name:
+
+/*
************************************************************************
*/
+/* These routines write to the special purpose
registers in the ColdFire */
+/* core. Since these registers are write-only in the
supervisor model, no */
+/* corresponding read routines exist.
*/
+
+FUNC_START(mcf5282_wr_mbar)
+ move.l 4(%sp),%d0
+ movec %d0,%mbar
+ nop
+ rts
+
+##=============================================================================
+##=============================================================================
+
+
Index:
packages/hal/m68k/mcf52xx/mcf5282/proc/current/src/proc_intr.c
===================================================================
RCS file:
packages/hal/m68k/mcf52xx/mcf5282/proc/current/src/proc_intr.c
diff -N
packages/hal/m68k/mcf52xx/mcf5282/proc/current/src/proc_intr.c
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++
packages/hal/m68k/mcf52xx/mcf5282/proc/current/src/proc_intr.c
1 Jan 1970 00:00:00 -0000
@@ -0,0 +1,176 @@
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded
Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red
Hat, Inc.
+//
+// eCos is free software; you can redistribute it
and/or modify it under
+// the terms of the GNU General Public License as
published by the Free
+// Software Foundation; either version 2 or (at your
option) any later version.
+//
+// eCos is distributed in the hope that it will be
useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of
MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU
General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General
Public License along
+// with eCos; if not, write to the Free Software
Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307
USA.
+//
+// As a special exception, if other files instantiate
templates or use macros
+// or inline functions from this file, or you compile
this file and link it
+// with other works to produce a work based on this
file, this file does not
+// by itself cause the resulting work to be covered
by the GNU General Public
+// License. However the source code for this file
must still be made available
+// in accordance with section (3) of the GNU General
Public License.
+//
+// This exception does not invalidate any other
reasons why a work based on
+// this file might be covered by the GNU General
Public License.
+//
+// Alternative licenses for eCos may be arranged by
contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+
+#include <cyg/infra/cyg_type.h>
+#include <cyg/infra/cyg_ass.h>
+#include <pkgconf/hal.h>
+#include <cyg/hal/hal_startup.h>
+#include <cyg/hal/hal_memmap.h>
+#include <cyg/hal/hal_arch.h>
+#include <cyg/hal/hal_intr.h>
+
+// Block the interrupt associated with the given
vector. To do this, we
+// write a 1 to the interrupt mask register bit.
Disable all interrupts while we access the
+// hardware registers.
+void hal_interrupt_mask(int _vector_)
+{
+ cyg_uint32 _vec_offset;
+ CYG_INTERRUPT_STATE _intr_state;
+
+ CYG_ASSERT(((_vector_) >= (HAL_PROG_INTC0_VEC_BASE +
1)) &&
+ ((_vector_) < (HAL_PROG_INTC1_VEC_BASE + 63))
+ , "Invalid vector");
+
+ if((_vector_) >= (HAL_PROG_INTC0_VEC_BASE + 1) &&
(_vector_) < HAL_PROG_INTC1_VEC_BASE)
+ {
+ _vec_offset = (_vector_) - HAL_PROG_INTC0_VEC_BASE;
/* should give us 1-63 */
+ HAL_DISABLE_INTERRUPTS(_intr_state);
+ if(_vec_offset <= 31)
+ MCF5282_SIM->intc[0].imrl |= (1 << _vec_offset);
+ else
+ MCF5282_SIM->intc[0].imrh |= (1 << (_vec_offset -
32));
+ HAL_RESTORE_INTERRUPTS(_intr_state);
+ }
+ else if((_vector_) >= (HAL_PROG_INTC1_VEC_BASE + 1)
&& (_vector_) < (HAL_PROG_INTC1_VEC_BASE + 63))
+ {
+ _vec_offset = (_vector_) - HAL_PROG_INTC1_VEC_BASE;
/* should give us 1-63 */
+ HAL_DISABLE_INTERRUPTS(_intr_state);
+ if(_vec_offset <= 31)
+ MCF5282_SIM->intc[1].imrl |= (1 << _vec_offset);
+ else
+ MCF5282_SIM->intc[1].imrh |= (1 << (_vec_offset -
32));
+ HAL_RESTORE_INTERRUPTS(_intr_state);
+ }
+}
+
+// Unblock the interrupt associated with the
given vector. Clear the
+// interrupt mask register bit. Disable all
interrupts while we access the
+// hardware registers.
+void hal_interrupt_unmask(int _vector_)
+{
+ cyg_uint32 _vec_offset;
+ CYG_INTERRUPT_STATE _intr_state;
+
+ CYG_ASSERT(((_vector_) >= (HAL_PROG_INTC0_VEC_BASE +
1)) &&
+ ((_vector_) < (HAL_PROG_INTC1_VEC_BASE + 63))
+ , "Invalid vector");
+
+ if((_vector_) >= (HAL_PROG_INTC0_VEC_BASE + 1) &&
(_vector_) < HAL_PROG_INTC1_VEC_BASE)
+ {
+ _vec_offset = (_vector_) - HAL_PROG_INTC0_VEC_BASE;
/* should give us 1-63 */
+
+ HAL_DISABLE_INTERRUPTS(_intr_state);
+
+ if(_vec_offset <= 31)
+ MCF5282_SIM->intc[0].imrl &= (~((1 << _vec_offset)
| 1));
+ else
+ MCF5282_SIM->intc[0].imrh &= (~((1 << (_vec_offset
- 32)) | 1));
+
+ HAL_RESTORE_INTERRUPTS(_intr_state);
+ }
+ else if((_vector_) >= (HAL_PROG_INTC1_VEC_BASE + 1)
&& (_vector_) < (HAL_PROG_INTC1_VEC_BASE + 63))
+ {
+ _vec_offset = (_vector_) - HAL_PROG_INTC1_VEC_BASE;
/* should give us 1-63 */
+
+ HAL_DISABLE_INTERRUPTS(_intr_state);
+
+ if(_vec_offset <= 31)
+ MCF5282_SIM->intc[1].imrl &= (~((1 << _vec_offset)
| 1));
+ else
+ MCF5282_SIM->intc[1].imrh &= (~((1 << (_vec_offset
- 32)) | 1));
+
+ HAL_RESTORE_INTERRUPTS(_intr_state);
+ }
+}
+
+// Acknowledge the interrupt by writing a
1 to the corresponding
+// interrupt pending bit. Write 0 to all other
interrupt pending bits. Leave
+// all priority levels unchanged. Disable all
interrupts while we access the
+// hardware registers.
+void hal_interrupt_acknowledge(int _vector_)
+{
+ CYG_ASSERT(((_vector_) >= (HAL_PROG_INTC0_VEC_BASE +
1)) &&
+ ((_vector_) < (HAL_PROG_INTC1_VEC_BASE + 63))
+ , "Invalid vector");
+
+ switch(_vector_)
+ {
+ case CYGNUM_HAL_VECTOR_UART0:
+
+ break;
+ default:
+ CYG_ASSERT(0, "intterupt not acknowledged");
+ }
+}
+
+// Set/clear the interrupt transition
register bit. Disable all
+// interrupts while we access the hardware registers.
+void hal_interrupt_configure(int _vector_, int
_level_, int _up_)
+{
+
+}
+
+// Set the priority in the interrupt control
register.
+// Disable all interrupts while we access the
hardware registers.
+void hal_interrupt_set_level(int _vector_, int
_prilevel_)
+{
+ cyg_uint32 _vec_offset;
+ CYG_INTERRUPT_STATE _intr_state;
+
+ CYG_ASSERT(((_vector_) >= (HAL_PROG_INTC0_VEC_BASE +
1)) &&
+ ((_vector_) < (HAL_PROG_INTC1_VEC_BASE + 63))
+ , "Invalid vector");
+
+ if((_vector_) >= (HAL_PROG_INTC0_VEC_BASE + 1) &&
(_vector_) < HAL_PROG_INTC1_VEC_BASE)
+ {
+ _vec_offset = (_vector_) - HAL_PROG_INTC0_VEC_BASE;
/* should give us 1-63 */
+
+ HAL_DISABLE_INTERRUPTS(_intr_state);
+
+ MCF5282_SIM->intc[0].icrn[_vec_offset] =
(u8_t)_prilevel_;
+
+ HAL_RESTORE_INTERRUPTS(_intr_state);
+ }
+ else if((_vector_) >= (HAL_PROG_INTC1_VEC_BASE + 1)
&& (_vector_) < (HAL_PROG_INTC1_VEC_BASE + 63))
+ {
+ _vec_offset = (_vector_) - HAL_PROG_INTC1_VEC_BASE;
/* should give us 1-63 */
+
+ HAL_DISABLE_INTERRUPTS(_intr_state);
+
+ MCF5282_SIM->intc[1].icrn[_vec_offset] =
(u8_t)_prilevel_;
+
+ HAL_RESTORE_INTERRUPTS(_intr_state);
+ }
+}
Index:
packages/hal/m68k/mcf52xx/mcf5282/proc/current/src/proc_misc.c
===================================================================
RCS file:
packages/hal/m68k/mcf52xx/mcf5282/proc/current/src/proc_misc.c
diff -N
packages/hal/m68k/mcf52xx/mcf5282/proc/current/src/proc_misc.c
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++
packages/hal/m68k/mcf52xx/mcf5282/proc/current/src/proc_misc.c
1 Jan 1970 00:00:00 -0000
@@ -0,0 +1,54 @@
+//==========================================================================
+//
+// proc_misc.c
+//
+// HAL implementation miscellaneous functions
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded
Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red
Hat, Inc.
+//
+// eCos is free software; you can redistribute it
and/or modify it under
+// the terms of the GNU General Public License as
published by the Free
+// Software Foundation; either version 2 or (at your
option) any later version.
+//
+// eCos is distributed in the hope that it will be
useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of
MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU
General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General
Public License along
+// with eCos; if not, write to the Free Software
Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307
USA.
+//
+// As a special exception, if other files instantiate
templates or use macros
+// or inline functions from this file, or you compile
this file and link it
+// with other works to produce a work based on this
file, this file does not
+// by itself cause the resulting work to be covered
by the GNU General Public
+// License. However the source code for this file
must still be made available
+// in accordance with section (3) of the GNU General
Public License.
+//
+// This exception does not invalidate any other
reasons why a work based on
+// this file might be covered by the GNU General
Public License.
+//
+// Alternative licenses for eCos may be arranged by
contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+
+#include <pkgconf/hal.h>
+#include <cyg/infra/cyg_type.h>
+
+#include <cyg/hal/proc_arch.h>
+#include <cyg/hal/hal_memmap.h>
+
+// Define the global pointer to the SIM
registers.
+
+volatile mcf5282_sim_t * const mcf5282_sim_p =
(mcf5282_sim_t *)MCF5282_MBAR;
+
+//--------------------------------------------------------------------------
+// End of var_misc.c
+
Index:
packages/hal/m68k/mcf52xx/mcf5282/proc/current/src/proc_startup.c
===================================================================
RCS file:
packages/hal/m68k/mcf52xx/mcf5282/proc/current/src/proc_startup.c
diff -N
packages/hal/m68k/mcf52xx/mcf5282/proc/current/src/proc_startup.c
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++
packages/hal/m68k/mcf52xx/mcf5282/proc/current/src/proc_startup.c
1 Jan 1970 00:00:00 -0000
@@ -0,0 +1,68 @@
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded
Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red
Hat, Inc.
+//
+// eCos is free software; you can redistribute it
and/or modify it under
+// the terms of the GNU General Public License as
published by the Free
+// Software Foundation; either version 2 or (at your
option) any later version.
+//
+// eCos is distributed in the hope that it will be
useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of
MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU
General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General
Public License along
+// with eCos; if not, write to the Free Software
Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307
USA.
+//
+// As a special exception, if other files instantiate
templates or use macros
+// or inline functions from this file, or you compile
this file and link it
+// with other works to produce a work based on this
file, this file does not
+// by itself cause the resulting work to be covered
by the GNU General Public
+// License. However the source code for this file
must still be made available
+// in accordance with section (3) of the GNU General
Public License.
+//
+// This exception does not invalidate any other
reasons why a work based on
+// this file might be covered by the GNU General
Public License.
+//
+// Alternative licenses for eCos may be arranged by
contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+
+#include <cyg/infra/cyg_type.h>
+#include <pkgconf/hal.h>
+#include <cyg/hal/hal_startup.h>
+#include <cyg/hal/hal_memmap.h>
+#include <cyg/hal/hal_arch.h>
+#include <cyg/hal/hal_intr.h>
+
+/*****************************************************************************
+proc_reset -- Processor-specific reset vector
initialization routine
+
+ This routine must be called with interrupts
disabled.
+
+INPUT:
+
+OUTPUT:
+
+RETURN VALUE:
+
+ None
+
+*****************************************************************************/
+void proc_reset(void)
+{
+ // Set up the mapping of our internal
registers. The LSB indicates that
+ // the registers are valid.
+
+ //mcf5282_wr_mbar((CYG_WORD32)(MCF5282_MBAR |
1));
+
+ // Do any platform-specific reset
initialization.
+
+ plf_reset();
+}
+
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