From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 23503 invoked by alias); 28 Mar 2011 10:47:03 -0000 Received: (qmail 23495 invoked by uid 22791); 28 Mar 2011 10:47:02 -0000 X-SWARE-Spam-Status: No, hits=4.9 required=5.0 tests=AWL,BAYES_00,BOTNET,DKIM_ADSP_CUSTOM_MED,FREEMAIL_FROM,NML_ADSP_CUSTOM_MED,RDNS_NONE,SPF_NEUTRAL X-Spam-Check-By: sourceware.org Received: from Unknown (HELO postoffice.kontron.pl) (217.153.153.214) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Mon, 28 Mar 2011 10:46:57 +0000 Received: from postoffice.kontron (localhost [127.0.0.1]) by postoffice.kontron.pl (Postfix) with ESMTP id 773401201AF; Mon, 28 Mar 2011 12:46:55 +0200 (CEST) Received: from jerzdy.rnd.kontron.pl (unknown [192.168.3.20]) by postoffice.kontron.pl (Postfix) with ESMTP id 6BEFB1201AD; Mon, 28 Mar 2011 12:46:55 +0200 (CEST) From: jerzy dyrda To: ecos-devel@ecos.sourceware.org, "Gian Maria" Date: Mon, 28 Mar 2011 10:47:00 -0000 User-Agent: KMail/1.9.9 References: <23118906-1707f2ce17e92d08d3084915122281bc@pkn7.m5r2.onet> In-Reply-To: <23118906-1707f2ce17e92d08d3084915122281bc@pkn7.m5r2.onet> MIME-Version: 1.0 Message-ID: <201103281246.55061.jerzdy@gmail.com> Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 7bit Subject: Re: STM32F107 on STM3210C-EVAL X-Anti-Virus: Kaspersky Anti-Virus for Linux Mail Server 5.6.26/RELEASE build 1, bases: 20110328 #5135518, check: 20110328 notchecked X-IsSubscribed: yes Mailing-List: contact ecos-devel-help@ecos.sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Post: List-Help: , Sender: ecos-devel-owner@ecos.sourceware.org X-SW-Source: 2011-03/txt/msg00036.txt.bz2 Hello all, On Monday 28 March 2011 11:51:45 qber_@poczta.onet.pl wrote: (...) > There is only one thing left - the RCC differences. In RM there is a > seperate section about RCC config for CL. But at the first look it seems > that registers are compatible. RCC registers are extended to support 2 extra PPL's with appropriate divider and multiplier. Main differences is that source of PLL clock it isn't anymore taken directly from HSE or HSE/2 clock but it's introduced new divider PREDIV1 thus PLLSRC bit in RCC_CFGR register has partially different meaning. And another issue is external crystal. It value is 25MHz not 8 MHz like in STM3210E what causes need of using second PLL to produce CPU 72MHz. HSE == 25MHz / PREDIV2 == 5 -> 5MHz * PLLMUL2 == 8 -> 40MHz / PREDIV1 == 5 -> 8MHz * PLLMUL == 9 -> 72MHz = SYSCLK It's looks ugly but above method it's used in ST source code for STM3210C evaluation board. Best regards jerzy