From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 11617 invoked by alias); 28 Mar 2011 11:23:12 -0000 Received: (qmail 11609 invoked by uid 22791); 28 Mar 2011 11:23:11 -0000 X-SWARE-Spam-Status: No, hits=-1.1 required=5.0 tests=AWL,BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,RCVD_IN_DNSWL_NONE,RFC_ABUSE_POST,T_RP_MATCHES_RCVD X-Spam-Check-By: sourceware.org Received: from smtpo21.poczta.onet.pl (HELO smtpo21.poczta.onet.pl) (213.180.142.152) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Mon, 28 Mar 2011 11:23:06 +0000 Received: from pkn7.m5r2.onet (pkn7.m5r2.onet [10.174.32.168]) by smtp.poczta.onet.pl (Onet) with ESMTP id 1482420121207; Mon, 28 Mar 2011 13:18:16 +0200 (CEST) Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received: from [217.6.141.85] by pkn7.m5r2.onet via HTTP id 201102281318141058010001; Mon, 28 Mar 2011 13:18:15 +0200 From: qber_@poczta.onet.pl To: ecos-devel@ecos.sourceware.org, Gian Maria , jerzy dyrda Date: Mon, 28 Mar 2011 11:23:00 -0000 Message-Id: <23137663-1e0ca441f77eb82df61226bca1165220@pkn7.m5r2.onet> Subject: RE: Re: STM32F107 on STM3210C-EVAL X-Onet-PMQ: ;217.6.141.85;DE;3 X-IsSubscribed: yes Mailing-List: contact ecos-devel-help@ecos.sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Post: List-Help: , Sender: ecos-devel-owner@ecos.sourceware.org X-SW-Source: 2011-03/txt/msg00037.txt.bz2 Hello again W dniu 2011-03-28 12:47:07 u=C5=BCytkownik jerzy dyrda n= apisa=C5=82: > Hello all, >=20 > On Monday 28 March 2011 11:51:45 qber_@poczta.onet.pl wrote: > (...) > > There is only one thing left - the RCC differences. In RM there is a > > seperate section about RCC config for CL. But at the first look it seems > > that registers are compatible. > RCC registers are extended to support 2 extra PPL's with appropriate divi= der and multiplier. > Main differences is that source of PLL clock it isn't anymore taken direc= tly from HSE or HSE/2 clock=20 > but it's introduced new divider PREDIV1 thus PLLSRC bit in RCC_CFGR regis= ter has partially=20 > different meaning. And another issue is external crystal. It value is 25M= Hz not 8 MHz like in=20 > STM3210E what causes need of using second PLL to produce CPU 72MHz. >=20 > HSE =3D=3D 25MHz / PREDIV2 =3D=3D 5 -> 5MHz * PLLMUL2 =3D=3D 8 ->= =20=20 > 40MHz / PREDIV1 =3D=3D 5 -> 8MHz * PLLMUL =3D=3D 9 -> 72MHz =3D SYSCLK >=20 > It's looks ugly but above method it's used in ST source code for STM3210C= evaluation board. >=20 It's not quite true. According to scheme and RM the clock can be takien fro= m PLL2 or HSE directly. This is configured in RCC_CFGR2 bit 16 PREDIV1_SRC. Only the crystal have to be replaced on PCB. > Best regards > jerzy >=20 >=20 Best regards Qber