From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 25853 invoked by alias); 14 Apr 2011 10:59:22 -0000 Received: (qmail 25842 invoked by uid 22791); 14 Apr 2011 10:59:21 -0000 X-SWARE-Spam-Status: No, hits=-1.8 required=5.0 tests=BAYES_00,FREEMAIL_FROM,TW_XB,T_RP_MATCHES_RCVD,T_TO_NO_BRKTS_FREEMAIL X-Spam-Check-By: sourceware.org Received: from sam.nabble.com (HELO sam.nabble.com) (216.139.236.26) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Thu, 14 Apr 2011 10:59:15 +0000 Received: from isper.nabble.com ([192.168.236.156]) by sam.nabble.com with esmtp (Exim 4.69) (envelope-from ) id 1QAKGZ-0003bu-Aj for ecos-devel@ecos.sourceware.org; Thu, 14 Apr 2011 03:59:15 -0700 Message-ID: <31395908.post@talk.nabble.com> Date: Thu, 14 Apr 2011 10:59:00 -0000 From: mlazcoz To: ecos-devel@ecos.sourceware.org Subject: RE: Re: STM32F107 on STM3210C-EVAL In-Reply-To: <23118906-1707f2ce17e92d08d3084915122281bc@pkn7.m5r2.onet> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable References: <23118906-1707f2ce17e92d08d3084915122281bc@pkn7.m5r2.onet> X-IsSubscribed: yes Mailing-List: contact ecos-devel-help@ecos.sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Post: List-Help: , Sender: ecos-devel-owner@ecos.sourceware.org X-SW-Source: 2011-04/txt/msg00006.txt.bz2 Hi Qber, I'm porting eCos to an STM3210C-eval fake board. I have started with system clocks until I've realized that all the job is already done by you! If you dont mind, could you send me a patch?=20 Thanks a lot, mlazcoz qber_ wrote: >=20 > Hi >=20 > W dniu 2011-03-26 12:07:30 u=C5=BCytkownik Ilija Kocho > napisa=C5=82: >> On 23.03.2011 11:50, John Dallaway wrote: >> > Hi Gian Maria >> > >> > Gian Maria wrote: >> > >> >> I'm porting eCos to STM3210C and I find a logical error on the >> >> implementation of CYGPKG_HAL_CORTEXM_STM32. >> >> CYGPKG_HAL_CORTEXM_STM32 must be the base of all STM32 uP and so is >> not >> >> correct for me to use >> >> >> >> cdl_option CYGHWR_HAL_CORTEXM_STM32 { >> >> display "STM32 variant in use" >> >> flavor data >> >> default_value {"F103ZE"} >> >> legal_values {"F103RC" "F103VC" "F103ZC" >> >> "F103RD" "F103VD" "F103ZD" >> >> "F103RE" "F103VE" "F103ZE" } >> >> description "The STM32 has several variants, the main >> differences >> >> being in the size of on-chip FLASH and SRAM >> >> and numbers of some peripherals. This option >> >> allows the platform HAL to select the >> specific >> >> microcontroller fitted." >> >> } >> >> >> >> That is inside >> "ecoscvs\ecos\packages\hal\cortexm\stm32\var\current\cdl", >> >> because with my EVB for example=20 >> >> the uP is a STM32F107VC. With this I can't set the right uP as default >> for >> >> the template. >> >> I'm right? I think the correct is to put the code inside >> >> "ecoscvs\ecos\packages\hal\cortexm\stm32\stm3210e_eval\current\cdl" >> > I am not sure I understand your question. Are you intending to create a >> > new platform HAL package for STM3210C-EVAL? >> > >> >> Can someone modify this so I can update my CVS and work with the right >> code? >> > It will be no problem to extend the set of legal values for >> > CYGHWR_HAL_CORTEXM_STM32. Of course, you can make this change in your >> > local CVS checkout until you are ready to contribute your platform >> > support for STM3210C-EVAL. >>=20 >> Current STM32 code, as is, would not work for single chip configuration >> as it unconditionally depends on external RAM. In SIvA we have an >> internal modification that enables single chip operation and if there is >> an interest we would post a patch. >>=20 > It seems from reference manual that STM32 familly is almost compatible. On > page 40 (RM) there is table with diffrences. The main issue is the > interenal RAM and FLASH memmory. The FLASH is not a big problem (probably > code will work just fine - I'm working with STM32103VD with settings for > VE), but the SRAM is a different matter. The stack is placed on the top of > internal SRAM memmory so you have to change the size of internal SRAM. > This can be done in > \packages\hal\cortexm\stm32\stm3210e_eval\current\include\pkgconf *.ldi > and *.h files. The build configuration for connectivity line have to be > set to ROM (Startup type) because this chip doesn't support FSMC. Next > thing to do is to modyfy the stm3210e_eval_misc.c (remove the FSMC > section). >=20 >=20 > base =3D CYGHWR_HAL_STM32_GPIOA; > HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_CRL, 0x88888888 ); > HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_CRH, 0x88888888 ); >=20=20=20=20=20 > base =3D CYGHWR_HAL_STM32_GPIOB; > HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_CRL, 0x88888888 ); > HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_CRH, 0x88888888 ); >=20=20=20=20=20 > base =3D CYGHWR_HAL_STM32_GPIOC; > HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_CRL, 0x88888888 ); > HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_CRH, 0x88888888 ); >=20=20=20=20=20 > base =3D CYGHWR_HAL_STM32_GPIOD; > HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_CRL, 0x88888888 ); > HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_CRH, 0x88888888 ); >=20=20=20=20=20 > // Set up GPIO lines for external bus >=20 > - base =3D CYGHWR_HAL_STM32_GPIOE; > - HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_CRL, 0xbbbbb4bb ); > - HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_CRH, 0xbbbbbbbb ); >=20 > - base =3D CYGHWR_HAL_STM32_GPIOF; > - HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_CRL, 0x44bbbbbb ); > - HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_CRH, 0xbbbb4444 ); >=20 > - base =3D CYGHWR_HAL_STM32_GPIOG; > - HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_CRL, 0x44bbbbbb ); > - HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_CRH, 0x44444bb4 ); >=20 >=20=20=20=20=20 > - // Set up FSMC NOR/SRAM bank 2 for NOR Flash >=20 > - base =3D CYGHWR_HAL_STM32_FSMC; >=20 > - HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_FSMC_BCR2, 0x00001059 ); > - HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_FSMC_BTR2, 0x10000705 ); >=20 > - // Set up FSMC NOR/SRAM bank 3 for SRAM >=20 > - HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_FSMC_BCR3, 0x00001011 ); > - HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_FSMC_BTR3, 0x00000200 ); >=20 >=20 > There is only one thing left - the RCC differences. In RM there is a > seperate section about RCC config for CL. But at the first look it seems > that registers are compatible. >=20 > Summary I think that for CL there is no need for creating new port but to > modyfy existing one for new internal FLASH and SRAM and without FSMC > module. >=20 > P.S. > If some is intereseted I have driver for UART with REMAP option and SYNC > mode. Also I have I2C driver. Both drivers are tested. >=20 > Best regards=20 > Qber >=20 >=20 >=20 >=20 >=20 >=20 --=20 View this message in context: http://old.nabble.com/STM32F107-on-STM3210C-E= VAL-tp31213227p31395908.html Sent from the Sourceware - ecos-devel mailing list archive at Nabble.com.