From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 15261 invoked by alias); 15 Oct 2009 15:43:38 -0000 Received: (qmail 15251 invoked by uid 22791); 15 Oct 2009 15:43:37 -0000 X-SWARE-Spam-Status: No, hits=-1.6 required=5.0 tests=AWL,BAYES_00 X-Spam-Check-By: sourceware.org Received: from top.few.vu.nl (HELO top.few.vu.nl) (130.37.20.4) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Thu, 15 Oct 2009 15:43:32 +0000 Received: from [130.37.30.42] (hppc190.cs.vu.nl [130.37.30.42]) by top.few.vu.nl with esmtp (Smail #115) id m1MySUE-0000BvC; Thu, 15 Oct 2009 17:43 +0200 Message-ID: <4AD7435B.3010105@cs.vu.nl> Date: Thu, 15 Oct 2009 15:43:00 -0000 From: Rutger Hofman User-Agent: Thunderbird 2.0.0.23 (X11/20090817) MIME-Version: 1.0 To: Jonathan Larmour CC: Ross Younger , eCos developers Subject: Re: NAND technical review References: <4AC6218C.20407@jifvik.org> <4ACB4B58.2040804@ecoscentric.com> <4ACC0722.9020601@jifvik.org> <4ACCC13F.40009@cs.vu.nl> <4AD69BBE.6070103@jifvik.org> In-Reply-To: <4AD69BBE.6070103@jifvik.org> Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit X-IsSubscribed: yes Mailing-List: contact ecos-devel-help@ecos.sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Post: List-Help: , Sender: ecos-devel-owner@ecos.sourceware.org X-SW-Source: 2009-10/txt/msg00026.txt.bz2 Jonathan Larmour wrote: >>> Does your implementation _require_ a BBT in its current >>> implementation? For simpler NAND usage, it may be overkill e.g. an >>> application where the number of rewrites is very small, so the >>> factory bad markers may be considered sufficient. >> >> This is a bit hairy in my opinion, and one reason is that there is no >> Standard Layout for the spare areas. One case where a BBT is forced: >> my BlackFin NFC can be used to boot from NAND, but it enforces a spare >> layout that is incompatible with MTD or anybody. It is even >> incompatible with most chips' specification that the first byte of >> spare in the first page of the block is the Bad Block Marker. >> BlackFin's boot layout uses this first byte in a way that suits it, >> and it may be 0 -- which would otherwise mean Bad Block. > > I infer that your layer can cope with that? I didn't see the handling > for that in io_nand_chip_bad_block.c. Well, I think I didn't answer this appropriately after all. This is not a chip issue but a controller issue (I am the needle stuck in the groove). The issue is that the BlackFin NFC (in its boot mode only!) enforces a deviant spare layout, which introduces an incompatibility between controller and any chips: the booting controller thinks it can arbitrarily use byte 0 of the first page's spare, and for chips that is usually the bad-block marker. One observation: the BlackFin NFC boots from page 0 (on block 0) and NAND chips usually guarantee that block 0 is not bad. Chips may even have a specified higher write-count-before-errors for block 0 than the other blocks. I think the chip manufacturers' motivation is to facilitate special handling of block 0: boot code, FIS, BBT, anything... Another observation: even though block 0 is not bad whatever the marker written by the boot code, it ought to be marked BAD_RESERVED in the BBT to avoid accidental erasure. Rutger