From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 15854 invoked by alias); 22 Dec 2010 13:37:48 -0000 Received: (qmail 15841 invoked by uid 22791); 22 Dec 2010 13:37:47 -0000 X-SWARE-Spam-Status: No, hits=-0.5 required=5.0 tests=AWL,BAYES_00,RCVD_IN_RP_RNBL,RDNS_DYNAMIC,TW_KG X-Spam-Check-By: sourceware.org Received: from ctel-78-157-16-61.cabletel.com.mk (HELO relay.cabletel.com.mk) (78.157.16.61) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Wed, 22 Dec 2010 13:37:40 +0000 Received: from [192.168.209.21] (unknown [92.53.40.73]) by relay.cabletel.com.mk (Postfix) with ESMTP id 240ACBEE71 for ; Wed, 22 Dec 2010 14:39:10 +0100 (CET) Message-ID: <4D11FF19.6000304@siva.com.mk> Date: Wed, 22 Dec 2010 13:37:00 -0000 From: Ilija Kocho User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.2.13) Gecko/20101208 Lightning/1.0b2 Thunderbird/3.1.7 ThunderBrowse/3.3.4 MIME-Version: 1.0 To: eCos developers Subject: Cortex-M Vector Table Offset Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-CableTel-MailScanner-Information: Please contact the ISP for more information X-CableTel-MailScanner-ID: 240ACBEE71.ACCA3 X-CableTel-MailScanner: Found to be clean X-CableTel-MailScanner-SpamScore: s X-IsSubscribed: yes Mailing-List: contact ecos-devel-help@ecos.sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Post: List-Help: , Sender: ecos-devel-owner@ecos.sourceware.org X-SW-Source: 2010-12/txt/msg00009.txt.bz2 Hello In a course of porting eCos to Cortex-M based devices, other than STM32, an issue occurs that must be addressed. The problem (In following discussion I refer to ROM start-up configuration): In current Cortex-M port the Vector Table Offset is fixed (VTOR set) by architecture port to 0x20000000 (CYGARC_REG_NVIC_VTOR_TBLBASE_SRAM defined in hal/cortexm/arch//include/hal_io.h). This is the place where it should be expected but on some devices this is not possible: The example is NXP LPC 17xx family that has no RAM in Data (SRAM) partition (i.e. at 0x20000000). Instead SRAM is located within Code partition at address 0x10000000. Proposed solution: Define Vector Table base (CYGARC_REG_NVIC_VTOR_TBLBASE_SRAM) in the variant with override option for the platform: respective var_io.h and/or plf_io.h. Also there is apparent dependence between CYGARC_REG_NVIC_VTOR_TBLBASE_SRAM and devices' memory configuration(s) so we could consider some shared defines with pkgconf files and/or CDL. This could provide flexibility useful for some other devices such as Freescale Kinetis family. Patch(es) should be easy and harmless. I could produce ones after discussion. For the end I have one question: What is use of CYGARC_REG_NVIC_VTOR_TBLOFF(0) (hal/cortexm/arch/current/src/hal_misc.c) Best regards Ilija