From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 477 invoked by alias); 23 Jun 2011 09:58:50 -0000 Received: (qmail 467 invoked by uid 22791); 23 Jun 2011 09:58:49 -0000 X-SWARE-Spam-Status: No, hits=0.4 required=5.0 tests=AWL,BAYES_20,RCVD_IN_DNSWL_NONE X-Spam-Check-By: sourceware.org Received: from anchor-post-1.mail.demon.net (HELO anchor-post-1.mail.demon.net) (195.173.77.132) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Thu, 23 Jun 2011 09:58:33 +0000 Received: from calivar.demon.co.uk ([83.104.54.243] helo=calivar.com) by anchor-post-1.mail.demon.net with esmtp (Exim 4.69) id 1QZggC-0006Mt-hD for ecos-devel@ecos.sourceware.org; Thu, 23 Jun 2011 09:58:32 +0000 Received: from [10.0.1.1] (daikon.calivar.com [10.0.1.1]) (using TLSv1 with cipher DHE-RSA-CAMELLIA256-SHA (256/256 bits)) (No client certificate requested) by calivar.com (Postfix) with ESMTPS id 27A5C19F6F7 for ; Thu, 23 Jun 2011 10:58:31 +0100 (BST) Message-ID: <4E030E46.8070700@calivar.com> Date: Thu, 23 Jun 2011 09:58:00 -0000 From: Nick Garnett User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-GB; rv:1.9.2.17) Gecko/20110414 SUSE/3.1.10 Thunderbird/3.1.10 MIME-Version: 1.0 To: ecos-devel@ecos.sourceware.org Subject: Re: Thread stack alignment requirements for ARM References: In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Mailing-List: contact ecos-devel-help@ecos.sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Post: List-Help: , Sender: ecos-devel-owner@ecos.sourceware.org X-SW-Source: 2011-06/txt/msg00019.txt.bz2 On 23/06/11 03:37, Michael Bergandi wrote: > Hi all, > > I am hoping that someone can share some knowledge on thread stack > alignment requirements for ARM targets and how eCos is handling it. > > According to the ARM site, they say that stacks should be 16 byte > aligned. Then, they go on to say that there are a couple ways that > stack alignment requirement can be managed. One of which was if you > are running on an OS and the OS has taken steps to ensure the > requirement is met, then the application need not worry about it. I > don't think I fully understand what this means exactly. > > Our particular target is the mx27 (ARM9). Out of habit, we make all > the memory for the thread stacks in our applications 4 byte aligned. > Is this enough? Is it really necessary? > > I have found some packages in the kernel (specifically, bsd_tcpip) > that has thread stack memory allocated with no alignment attribute > set. This got me wondering how this all works. > > I would love to here from someone with a much better grasp on this. > The alignment of the pieces of memory that are used as stacks does not really matter. It is the alignment of the stack pointer that matters. This is handled in HAL_THREAD_INIT_CONTEXT() which ensures that the stack pointer is 16 byte aligned regardless of the alignment of the stack pointer passed to it. -- Nick Garnett eCos Kernel Architect eCosCentric Limited http://www.eCosCentric.com The eCos experts Barnwell House, Barnwell Drive, Cambridge, UK. Tel: +44 1223 245571 Registered in England and Wales: Reg No: 4422071