RE: How to handle very fast repeating interrupts?

["Chris Zimman" <czimman@bloomberg.com>]

> Is the FIQ interrupt disabled while scheduling? (And if so - is it
> disabled that long time?) I hope it isn't ...
> The only RT requirement is to read the data from the memory bus
> 12us after the interrupt at the latest. The processing afterwards
> can be done in non-RT.

Interrupts have to be disabled while you're in an ISR, and since the
scheduler is typically driven from a timer interrupt, you are going to run
into that.
I would be concerned that the time it takes to schedule anything may
interfere with the RT window that you need to operate in.

Not being familiar with your project, I can't really say, but if I were to
design something that needed this level of RT performance, I would probably
use a faster processor or a small CPLD/FPGA to help with the data
acquisition.

> I'd like to read the data out of the buffer in a thread to filter and
> store it afterwards. So I need some sort of external accessable buffer.
> I imagine that the FIQ stores the data into a ring buffer and a normal
> eCos thread is going to read out and process the data which accumulated
> in the buffer since the last time.

That's fine -- this can work just the way you want it to.

> Do I really have to use the _fiq appendix for the registers in the FIQ?
> Anyway - this is very like I'd try it. But since a thread has to access
> the buffer I have to implement a ringbuffer. (Because it could be
> interrupted by the FIQ and this would overwrite the data in the buffer
and/or
> corrupt the counter.) And I don't need the loop since there is only one
data
> word I have to fetch each time.

No, the _fiq appendix was just for the purposes of clarity in this example.  

The particulars of how you want to implement this are of course up to you and
beyond the scope of this general discussion.

--Chris