From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 15920 invoked by alias); 21 Sep 2011 00:43:22 -0000 Received: (qmail 15908 invoked by uid 22791); 21 Sep 2011 00:43:20 -0000 X-SWARE-Spam-Status: No, hits=-2.1 required=5.0 tests=AWL,BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FROM,RCVD_IN_DNSWL_LOW,TW_DR X-Spam-Check-By: sourceware.org Received: from mail-fx0-f49.google.com (HELO mail-fx0-f49.google.com) (209.85.161.49) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Wed, 21 Sep 2011 00:43:06 +0000 Received: by fxg7 with SMTP id 7so1418065fxg.36 for ; Tue, 20 Sep 2011 17:43:05 -0700 (PDT) MIME-Version: 1.0 Received: by 10.223.75.24 with SMTP id w24mr2196457faj.132.1316565785052; Tue, 20 Sep 2011 17:43:05 -0700 (PDT) Received: by 10.223.114.211 with HTTP; Tue, 20 Sep 2011 17:43:05 -0700 (PDT) Date: Wed, 21 Sep 2011 00:43:00 -0000 Message-ID: Subject: cyg_drv_dsr_lock usage From: Michael Bergandi To: eCos Developer List Content-Type: text/plain; charset=ISO-8859-1 X-IsSubscribed: yes Mailing-List: contact ecos-devel-help@ecos.sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Post: List-Help: , Sender: ecos-devel-owner@ecos.sourceware.org X-SW-Source: 2011-09/txt/msg00003.txt.bz2 Hi all, I have recently written an eCos I2C driver for a Freescale mx27 processor. The driver is working. However, I have some questions whether what I have done is the right way or if I have used some calls incorrectly. cyg_drv_drs_lock and unlock are of particular interest. I referenced the existing i2c_mcf52xx and i2c_lpc2xxx drivers as I was developing mine. The driver is pretty simple. It is probably most closely modeled after the lpc2xxx driver in that I do most of my work in the ISR, which is pretty minimal. Using a single byte TX as an example should give the idea. The cyg_i2c_tx call is received by the driver with the usual parameters. I2C module is setup and enabled with interrupts. The slave address is shifted with the read/write bit set. Send the start signal. Send the slave address. I2C module interrupts. In the ISR, if the address was acked, I send the data byte, exit ISR. Get the next interrupt from the ISR. Set the completion flag, signal the DSR to notify the driver the transaction is finished. After the transaction was kicked off by sending the address, the driver then waits for the transaction to finish in this call: static void wait_for_xfer_completion(cyg_mxc_i2c_extra_t *extra) { /* lock the driver and dsr and wait for the transfer to complete */ cyg_drv_mutex_lock(&extra->i2c_lock); cyg_drv_dsr_lock(); cyg_drv_interrupt_unmask(extra->i2c_isrvec); while (!(extra->i2c_flag & (I2C_FLAG_XFER_COMPLETE | I2C_FLAG_ERROR))) { cyg_drv_cond_wait(&extra->i2c_wait); } cyg_drv_interrupt_mask(extra->i2c_isrvec); cyg_drv_dsr_unlock(); cyg_drv_mutex_unlock(&extra->i2c_lock); } My questions are: Does anyone see any problems with this? Is the DSR lock really necessary? Should this be ordered differently? One more note that may affect responses. This driver is used to handle both I2C buses with multiple devices on each bus. Thank you for any information you can provide. -- Mike