From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 19099 invoked by alias); 25 Nov 2010 11:19:14 -0000 Received: (qmail 18984 invoked by uid 22791); 25 Nov 2010 11:19:13 -0000 X-SWARE-Spam-Status: No, hits=-1.2 required=5.0 tests=AWL,BAYES_40,RCVD_IN_DNSWL_NONE X-Spam-Check-By: sourceware.org Received: from anchor-post-3.mail.demon.net (HELO anchor-post-3.mail.demon.net) (195.173.77.134) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Thu, 25 Nov 2010 11:19:08 +0000 Received: from calivar.demon.co.uk ([83.104.54.243] helo=xl5.calivar.com) by anchor-post-3.mail.demon.net with esmtp (Exim 4.69) id 1PLZqz-0004WN-oK; Thu, 25 Nov 2010 11:19:05 +0000 Received: from xl5.calivar.com (localhost [127.0.0.1]) by xl5.calivar.com (Postfix) with ESMTP id 49AD513870D; Thu, 25 Nov 2010 11:19:04 +0000 (GMT) To: Nagaraj K Cc: ecos-devel@ecos.sourceware.org Subject: Re: Cortex-M3 HAL interrupt-priority code bug References: From: Nick Garnett Original-Sender: nickg@ecoscentric.com Date: Thu, 25 Nov 2010 11:19:00 -0000 In-Reply-To: Message-ID: User-Agent: Gnus/5.09 (Gnus v5.9.0) Emacs/21.3 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Mailing-List: contact ecos-devel-help@ecos.sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Post: List-Help: , Sender: ecos-devel-owner@ecos.sourceware.org X-SW-Source: 2010-11/txt/msg00005.txt.bz2 Nagaraj K writes: > I see that this function wrongly implements the priority level in > Cortex-M3 processor. According to the Cortex-M3 data sheet, we need to > write the priority level to the top N bits of the register where N is > the number of priority level bits implemented in this particular > version of the cortex variant. The intention in the design of the hardware is that software can use a 256 level prioirity scheme on all implementations. By defining the actual priority in terms of the top N bits of the registers, the hardware essentially groups the 256 virtual priorities into a set of real priorities by ignoring the less significant bits. eCos simply follows the lead given by the hardware and implements 256 priorities. It is a good scheme and allows us to write code that will work in all implementations. -- Nick Garnett eCos Kernel Architect eCosCentric Limited http://www.eCosCentric.com The eCos experts Barnwell House, Barnwell Drive, Cambridge, UK. Tel: +44 1223 245571 Registered in England and Wales: Reg No: 4422071