From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 25030 invoked by alias); 16 Feb 2009 12:32:53 -0000 Received: (qmail 25006 invoked by uid 22791); 16 Feb 2009 12:32:48 -0000 X-SWARE-Spam-Status: No, hits=-3.3 required=5.0 tests=AWL,BAYES_00,RCVD_IN_DNSWL_LOW X-Spam-Check-By: sourceware.org Received: from mailout1.zih.tu-dresden.de (HELO mailout1.zih.tu-dresden.de) (141.30.67.72) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Mon, 16 Feb 2009 12:32:42 +0000 Received: from rmc67-31.zih.tu-dresden.de ([141.30.67.31] helo=server-n) by mailout1.zih.tu-dresden.de with esmtp (Exim 4.63) (envelope-from ) id 1LZ2eN-0004up-Kx for ecos-devel@ecos.sourceware.org; Mon, 16 Feb 2009 13:32:39 +0100 Received: from martin_pc.home (p5B0ED844.dip.t-dialin.net [91.14.216.68]) by server-n (Postfix) with ESMTP id 6C938100A08F for ; Mon, 16 Feb 2009 13:32:39 +0100 (CET) Date: Mon, 16 Feb 2009 12:32:00 -0000 To: "ecos-devel@ecos.sourceware.org" Subject: Re: How to handle very fast repeating interrupts? From: "Martin Laabs" Content-Type: text/plain; charset=iso-8859-1 MIME-Version: 1.0 References: Content-Transfer-Encoding: 7bit Message-ID: In-Reply-To: User-Agent: Opera Mail/9.51 (Linux) X-IsSubscribed: yes Mailing-List: contact ecos-devel-help@ecos.sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Post: List-Help: , Sender: ecos-devel-owner@ecos.sourceware.org X-SW-Source: 2009-02/txt/msg00007.txt.bz2 Hello, On Mon, 16 Feb 2009 13:08:34 +0100, Chris Zimman wrote: >> I use the scheduler... > > Then I'm surprised you're able to maintain the RT requirement that you need, > because it seems as that any scheduling or kernel event alone may be enough > to break it. Is the FIQ interrupt disabled while scheduling? (And if so - is it disabled that long time?) I hope it isn't ... The only RT requirement is to read the data from the memory bus 12us after the interrupt at the latest. The processing afterwards can be done in non-RT. >> I'd like to place the ring-buffer into the fast onchip sram. >> Can I just define some symbols in the linker script for that purpose? >> Or can I tell the assembler to generate some symbols in a special section >> like >> >> .section ".sram_data" >> _adc_buffer: >> .rept 64 >> .long 0 >> .endr >> _adc_buffer_start: >> .long 0 >> _adc_buffer_end: >> .long 0 > > You probably don't even need to do that unless you have other external code > that needs to deal with it. I'd like to read the data out of the buffer in a thread to filter and store it afterwards. So I need some sort of external accessable buffer. I imagine that the FIQ stores the data into a ring buffer and a normal eCos thread is going to read out and process the data which accumulated in the buffer since the last time. > I mean this is kind of a one-off, so pretty much any solution you come up > with that's fast works here. > > Can you do something like: > > my_FIQ_ISR: > [... FIQ setup ...] > > ldr r8_fiq, =ON_CHIP_SRAM > ldr r9_fiq, =ADC_READ_ADDR > ldr r10_fiq, #COUNT > 1: > ldr r11_fiq, [r9_fiq] > str r11_fiq, [r8_fiq], #4 > sub r10_fiq, r10_fiq, #1 > cmp r10_fiq, #0 > bne 1b > > [... cleanup/return ...] Do I really have to use the _fiq appendix for the registers in the FIQ? Anyway - this is very like I'd try it. But since a thread has to access the buffer I have to implement a ringbuffer. (Because it could be interrupted by the FIQ and this would overwrite the data in the buffer and/or corrupt the counter.) And I don't need the loop since there is only one data word I have to fetch each time. Thank you, Martin L.