RE: [ECOS] interrupts

["Geoff Patch" <grp@cea.com.au>]

Hi Guys,

> My problem has at this point elevated to the position where i am unsure of
> if the MPC850 is the right CPU choise for this application.
>
> In my application i will receive atleased 5000 interrupt/s which makes the
> context switch time a very large part of the systems total capacity. AFAIK
> then the VSR code handles _all_ interrupts, is that right? Is
> there any way
> of decreasing the latency on just one interrupt?


If you're going to be receiving interrupts at a *minimum* rate of 5 KHz,
then I think you're right to start thinking about another CPU.

> Just hypotheoretical - what performance would i get if i used a
> MPC823 that
> has four times that cache size that i have in the MPC850. Could i expect
> twice the performance of the 850....?

We use 50 KHz MPC860s with 4K I and D caches, and my feeling is that a 5 KHz
interrupt would cause real problems for these devices. I believe it's
possible to lock code into the caches (although we've never done it), but
even so, I think you'd still be in trouble.

Just my $0.02, and I'm sorry I can't offer anything more positive.


Good Luck


Geoff

-----------------------------
Geoff Patch
Senior Software Engineer
CEA Technologies
Canberra Australia
02-6213-0141


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