Re: [ECOS] Re: Basic question about porting to Xilinx PPC440

Re: [ECOS] Re: Basic question about porting to Xilinx PPC440

[Salvatore Lionetti]

Hi Mikhail,

Just for curiosity:
1) are you porting PPC440 ecos to Xilinx (so already have another port, es 405?) or are you working on PPC405 ecos to Xilinx?

2) Thanks but i can't understand your response: you say that ppc405 emulated start at 0xfffffffc, right? moreover you can't find any binary (neither file or procedure). So: how is possible to load an elf directly from reset vector? Reading the Xilinx doc i note that is possible to generate a .ace file containing also a .elf directly so:

3) is possible to instruct Xilinx tool to accept only a binary flash image and no elf at all?

have a good day





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Re: [ECOS] Re: Basic question about porting to Xilinx PPC440

[Mikhail Matusov]

Hi Salvatore,

> Just for curiosity:
> 1) are you porting PPC440 ecos to Xilinx (so already have another port, es 
> 405?) or are you working on PPC405 ecos to Xilinx?

Yes, I need to port eCos to Xilinx PPC440 (i.e. Virtex-5). There is a port 
to Xilinx PPC405 (Virtex-4) available from MIND, which hopefully can be used 
as a starting point.


> 2) Thanks but i can't understand your response: you say that ppc405 
> emulated start at 0xfffffffc, right? moreover you can't find any binary 
> (neither file or procedure). So: how is possible to load an elf directly 
> from reset vector? Reading the Xilinx doc i note that is possible to 
> generate a .ace file containing also a .elf directly so:
>
> 3) is possible to instruct Xilinx tool to accept only a binary flash image 
> and no elf at all?


Perhaps I didn't quite understand your question. There are many ways how to 
bootstrap the CPU and load an OS or an application in a Xilinx chip. The way 
we are doing it here is using a basic bootloader program. The bootloader is 
compiled into an .elf file and then merged with the hardware bitstream .bit 
file and the .bmm memory map file with the data2mem utility. This produces 
new .bit bitstream file which now includes the bootloader. Every time this 
file is loaded into the FPGA (we are using a separate CPLD to do this 
initial load) the bootloader is executed automatically (it starts from the 
0xFFFFFFFC address). The bootloader then goes to read another .elf file in 
SREC format from an external flash memory. That file holds our OS (which is 
currently VxWorks) and an application software.

I hope this helps.
/Mikhail


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Re: [ECOS] Re: Basic question about porting to Xilinx PPC440

[Mikhail Matusov]

Hi Salvatore,

Thanks for your response.

> [405 Board]
> For ppc405 porting, i've found that guide you post (many thanks) if 
> followed generates a demo.elf(mind emb dev) or redboot.elf(uni-padeborn)
> Is there a .bin image or procedure somewhere? Is ppc405 emulated from the 
> beginning of instruction fetching@0xFFFFFFFC?


I am not sure about binary image... I am actually yet to try building eCos 
for PPC405 myself. With regards to your last question, PPC405 does start 
execution from 0xFFFFFFFC on powerup.


/Mikhail


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[ECOS] Re: Basic question about porting to Xilinx PPC440

[Salvatore Lionetti]

Hi,

[ecos->xilinx ppc440]
Don't know

[440->450]
Many month ago, when i'm working with a salary, i've ported a boot (mixed ASM/C) from ppc440EP to ppc405GPr on a remote radio head for 4G with a proprietary os.
The raw porting IN MY CASE was simple:
- only few opcodes was incompatible by the 2 uP (like the instruction/data sync);
- some base address or peripheral controller max instance change (not the register relative offset, syntax and naming);
- ebc, i2c, ethernet controller look likes very similar;
- different internal clock frequency and pll

[Linux->Ecos]
Don't know

[405 Board]
For ppc405 porting, i've found that guide you post (many thanks) if followed generates a demo.elf(mind emb dev) or redboot.elf(uni-padeborn)
Is there a .bin image or procedure somewhere? Is ppc405 emulated from the beginning of instruction fetching@0xFFFFFFFC?

Have a good day




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