From mboxrd@z Thu Jan 1 00:00:00 1970 From: "Ling Su" To: "Nick Garnett" , "Jonathan Larmour" Cc: Subject: [ECOS] Fw: [ECOS] How to access PCI memory(HELP).... Date: Mon, 11 Sep 2000 21:05:00 -0000 Message-id: <00e101c01c6f$1c891f70$1201a8c0@crusoe> X-SW-Source: 2000-09/msg00147.html > Nick wrote, > > > > PCI_IOSPACE_BASE only maps PCI device IO registers, not memory > > mappings. I don't believe we actually use any of these mappings, which > > appear at 0x0C000000/0xAC000000 physical/logical addresses. > > > > We also use the master address windows. Window one is set up to map > > the 4372 control registers at 0x1C000000 in PCI space to > > 0x1C000000/0xBC000000 in the CPU. Window 2 maps 0x80000000 in PCI > > space to 0x80000000 physical which the MMU remaps to 0xC0000000 > > logical. However, the 4372 also occupies the first 256Mb of this. > > > [Ling] > You mean the south bridge chip also occupies 256MB space? Where I can find > this information? I didn't quite understand the MMU inialization part now, I > have to read the vr4300 manual to catch it. I agree that the part on PCI > address windows, you mean the first register is for mapping 4372 registers, > so the second register windows set for memory space on PCI bus, right? > > > So, if my reading of the code and documentation is correct, then > > HAL_PCI_PHYSICAL_MEMORY_BASE should be 0xD0000000, to skip the first > > 256Mb, and HAL_PCI_ALLOC_BASE_MEMORY should be 0x90000000. You should > > then be able to access PCI device memory from 0xD0000000. > > > > Why need I set HAL_PCI_ALLOC_BASE_MEMORY to 0x90000000, originally it is > 0x0, which means mapp the memory from the beginning, what is the rational to > add a 0x9000_0000 offset? > > > Of course currently the MMU only maps the first 256Mb of PCI space at > > 0xC0000000, so the MMU mapping needs to be extended. The simplest way > > to do this is to increase NUMB_PG in platform.S from 8 to 16. The > > current code appears to only use 16 of the 32 TLB entries, so using > > all 32 will give 512Mb of mapped PCI memory. > > > > > > Ling Su, please give this a try and if it works we can put these > > values into the standard sources. > > > > Nick, I follow your suggestion, basically I changed three things, > (1). HAL_PCI_PHYSICAL_MEMORY_BASE set to 0xD0000000 > (2). HAL_PCI_ALLOC_BASE_MEMORY set to 0x90000000 > (3). increase NUMB_PG to 16 > > Unfortunately it doesn't work, I append the the log in the end of this > message, what causes a SIGSEGV signal ususally? > Nick, I think I understand what Nick means, because 0x8000_0000 maps to 0xC000_0000, I should use 0x9000_0000 mapping to 0xD000_0000. Acutally last time, I made a mistake, I changed HAL_PCI_ALLOC_BASE_MEMORY to 0x0900_0000, not 0x9000_0000. So the result is, ---------------------------------------------------------------------------- ---------- BAR[0] 0x09000000 / probed size 0xFFF00000 / CPU addr 0xD9000000 ---------------------------------------------------------------------------- ---------- If I correct this mistake, I find ---------------------------------------------------------------------------- ---------- BAR[0] 0x90000000 / probed size 0xFFF00000 / CPU addr 0x60000000 ---------------------------------------------------------------------------- ---------- The CPU address 0x6000_0000 is 0xD000_0000 + 0x9000_0000 = 0x6000_0000, so there is a bug for "cyg_pci_allocate_memory_priv" in pci1.c, dev_info->base_map[bar] = (cyg_unit32) (aligned_addr+HAL_PHYSICAL_MEMORY_BASE) &0xFFFFFFFF where the aligned_addr = (*base+size-1) & ~(size - 1); *base is set to HAL_PCI_ALLOC_BASE_MEMORY as default, if I set HAL_PCI_ALLOC_BASE_MEMORY will be added on HAL_PHYSICAL_MEMORY_BASE for base_map. so it is not what I supposed, is that any understanding problem? I don't know what is the exact meaning for "HAL_PCI_ALLOC_BASE_MEMORY" and "HAL_PHYSICAL_MEMORY_BASE ", if what I think is true, I will change dev_info->base_map[bar] to (cyg_unit32) (aligned_addr + HAL_PHYSICAL_MEMORY_BASE - HAL_PCI_ALLOC_BASE_MEMORY) &0xFFFFFFFF Any suggestion, let me know, I will try this way first tomorrow. Thanks, -Ling