Re: [ECOS] Regarding to eCos on VRC4373

["Ling Su" <lingsu@palmmicro.com>]

> > <2>. We have some communication application developed on the board,
> > unfortunately the eCos defaultly in Big Endian mode for VRC4373. Since
> > communication application usually in Little Endian mode, I don't know
the
> > rational reason behind the Big Endian choice for this platform, and I
also
> > would like to know the possibility to compile eCos GDB stub and lib in
> > Little Endian mode, can we do it smoothly or need any hacking on the
source
> > code?
>
> You will probably need to make some adjustments in the platform code. But
> I believe the architecture and variant HALs should work because we have a
> v4300-based internal board that used to be little-endian if I remember
> right.
>

Can you disclouse which vr4300 based board is running eCos, I am just
curious since I didn't find any supported platform on eCos website except
the vrc4373 evaluation board.

I briefly checked the platform code, I didn't find any specific point to
modify since the Macro define CYG_LSBFIRST or CYG_MSBFIRST looks to me take
care of a lot of endian issues. I am just wondering why the Little Endian
mode is illegal for VR4300 platform. What I can think of doing first is to
try to enable it and make the monitor, is that doable?

Since I found the PMON comes together with NEC board is Little endian, can I
just complile the eCos lib in Little endian mode and debug it using PMON?
Any comments on this way? Thanks a lot!

-Ling