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From: "Krishna Ganugapati" <krishnag@marakicorp.com>
To: "Gary Thomas" <gary@mlbassoc.com>
Cc: <ecos-discuss@sources.redhat.com>
Subject: Re: [ECOS] Question on wigglers, debugging Redboot in flash forthe XScale target in single step mode
Date: Mon, 02 Aug 2004 15:15:00 -0000	[thread overview]
Message-ID: <064e01c478a3$219df960$6701a8c0@marakicorp.com> (raw)
In-Reply-To: <1091458778.12242.24.camel@hermes>

Gary, Thanks for the response.

I'm afraid I don't quite understand what you're saying..

a)  > Why do you think this is wrong?  When you reset the board, single
> stepping (via hardware which is very different that what you describe in
> item "c" above), you should execute the "reset handler" an instruction
> at a time.  This is just what is supposed to happen.

Are you saying that this is correct behavior?

When I hit the reset vector, I'm stuck.. subsequent single steps only keep
me at the reset vector - I don't advance any further..

b) How do I debug my redboot image?
-------------------------------------------------
----- Original Message ----- 
From: "Gary Thomas" <gary@mlbassoc.com>
To: "Krishna Ganugapati" <krishnag@marakicorp.com>
Cc: <ecos-discuss@sources.redhat.com>
Sent: Monday, August 02, 2004 7:59 AM
Subject: Re: [ECOS] Question on wigglers, debugging Redboot in flash forthe
XScale target in single step mode


> On Mon, 2004-08-02 at 08:49, Krishna Ganugapati wrote:
> > Hello,
> >
> > I'm looking for some clarification on the following issues.
> >
> > Target;: Custom IXP425 XScale (almost identical to the IXDP development
> > board, minus the highspeed UART and minus the LEDs), Redboot in ROM
mode.
> > Debugging interface:  Macraigor Wiggler, OCD Commander for the software
> > debugger on the host.
> >
> > Situation:  I can successfully download my redboot rom image to Flash
using
> > the Wiggler and the Macraigor Flash Programmer.
> > When I reset my target, I connect to the JTAG port using the OCD
Commander
> > debugger and attempt to single step through instructions.
> >
> > Results
> >
> > 1) Through the OCD Debugger, I note that Flash memory is correctly
relocated
> > at 0x000000000.
> > 2) Using the OCD Debugger, I can manual configure the SDRAM registers
and
> > determine that my SDRAM acc ANy recess is good. I flip the
> > EXP_BUS_CONFIGURATION bits that switc SDRAM and Flash around and
determine
> > that SDRAM is now located at 0x00000000 - I can successfully read and
write
> > words to the first 256 MB so I am assuming memory is good.
> >
> > 3) Reset the board, board is now in bootup mode, flash is at 0x00000000.
I
> > now attempt to single step through my redboot rom image. On the first
> > instruction, the board transfers control to the reset handler.
> >
> > Questions:
> >
> >  a) Has anyone seen behavior like this?
> > b) On the web it looks like quite a few people have seen something like
> > this, but there have been no followups on how to fix this.
> > c) When I reviewed the XScale documentation, it says that when a
debugger
> > executes a single step instruction, a debug event handler is expected
and
> > that this debug event handler is overloaded at the reset handler. It
also
> > says that the debug event handler code needs to be downloaded to the
target
> > through the JTAG. Questions:
> >     i) Does the OCD Commander software debugger  interface actually
download
> > a debug event handler? If it does, then my conclusions are wrong and I
have
> > to look elsewhere for why things in single step are not progressing, but
if
> > I'm right, then perhaps I need a more sophisticated debugger for my JTAG
> > interface (the OCD Commander is free). Any recommendations
>
> Why do you think this is wrong?  When you reset the board, single
> stepping (via hardware which is very different that what you describe in
> item "c" above), you should execute the "reset handler" an instruction
> at a time.  This is just what is supposed to happen.
>
> >
> > Other clarifications:
> > 1) One thing that was not very clear in XScale little endian vs big
endian
> > modes was the opcode fetch modes for the XScale. After investigating, my
> > understanding is that whether in big endian or in little endian mode,
> > XScale opcode fetches are always in little endian mode. Which is why
when
> > you build a big endian target for the XScale IXP425 board which
generates
> > the instructions in big endian mode, you need to byte swap the image. Is
> > this correct?
> >
> > Thanks for any input.
> >
> > Krishna
> -- 
> Gary Thomas <gary@mlbassoc.com>
> MLB Associates
>


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  reply	other threads:[~2004-08-02 15:15 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2004-07-21 10:52 [ECOS] Problems when aborting tftp transfers Øyvind Harboe
2004-08-02 13:01 ` Andrew Lunn
2004-08-02 13:45   ` Øyvind Harboe
2004-08-02 14:02     ` Andrew Lunn
2004-08-02 14:14       ` Øyvind Harboe
2004-08-02 14:27         ` Andrew Lunn
2004-08-02 14:49           ` [ECOS] Question on wigglers, debugging Redboot in flash for the XScale target in single step mode Krishna Ganugapati
2004-08-02 14:59             ` Gary Thomas
2004-08-02 15:15               ` Krishna Ganugapati [this message]
2004-08-02 15:21                 ` [ECOS] Question on wigglers, debugging Redboot in flash forthe " Gary Thomas
2004-08-02 16:51                   ` [ECOS] Question on wigglers, debugging Redboot in flash fortheXScale " Krishna Ganugapati
2004-08-03 15:59                   ` Krishna Ganugapati
2004-08-03  6:40       ` [ECOS] Problems when aborting tftp transfers Øyvind Harboe
2004-08-03  9:49         ` Andrew Lunn
2004-08-03  9:56           ` Øyvind Harboe

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