#ifndef CYGONCE_HAL_PLATFORM_SETUP_H #define CYGONCE_HAL_PLATFORM_SETUP_H /*============================================================================= // // hal_platform_setup.h // // Platform specific support for HAL (assembly code) // //============================================================================= //####ECOSGPLCOPYRIGHTBEGIN#### // ------------------------------------------- // This file is part of eCos, the Embedded Configurable Operating System. // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. // Copyright (C) 2003 Nick Garnett // // eCos is free software; you can redistribute it and/or modify it under // the terms of the GNU General Public License as published by the Free // Software Foundation; either version 2 or (at your option) any later version. // // eCos is distributed in the hope that it will be useful, but WITHOUT ANY // WARRANTY; without even the implied warranty of MERCHANTABILITY or // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License // for more details. // // You should have received a copy of the GNU General Public License along // with eCos; if not, write to the Free Software Foundation, Inc., // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. // // As a special exception, if other files instantiate templates or use macros // or inline functions from this file, or you compile this file and link it // with other works to produce a work based on this file, this file does not // by itself cause the resulting work to be covered by the GNU General Public // License. However the source code for this file must still be made available // in accordance with section (3) of the GNU General Public License. // // This exception does not invalidate any other reasons why a work based on // this file might be covered by the GNU General Public License. // // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. // at http://sources.redhat.com/ecos/ecos-license/ // ------------------------------------------- //####ECOSGPLCOPYRIGHTEND#### //============================================================================= //#####DESCRIPTIONBEGIN#### // // Author(s): gthomas // Contributors:gthomas, tdrury, nickg // Date: 2001-07-12 // Purpose: AT91/EB55 platform specific support routines // Description: // Usage: #include // //####DESCRIPTIONEND#### // //===========================================================================*/ #include //===========================================================================*/ .macro _pclock_init ldr r0,=AT91_PMC // Power saving interface ldr r1,=0xFFFFFFFF // Enable all peripheral [clocks] str r1,[r0,#AT91_PMC_PCER] .endm .macro _pio_init ldr r0,=AT91_PIOA // Disable PIO (so peripherals can use bits) ldr r1,=(0xffffffff) str r1,[r0,#AT91_PIO_PDR] .endm //===========================================================================*/ #if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM) #define AT91_PMC_CGMR_INIT0 (AT91_PMC_CGMR_MOSC_XTAL | \ AT91_PMC_CGMR_MOSC_ENA | \ AT91_PMC_CGMR_OSC_CNT(6)) // from IAR init code for EVB: // - div by 5 Fin = 3,6864 =(18,432 / 5) // - Mul 25+1: Fout = 95,8464 =(3,6864 *26) // for 96 MHz the error is 0.16% // Field out NOT USED = 0 // PLLCOUNT pll startup time esrtimate at : 0.844 ms // PLLCOUNT 28 = 0.000844 /(1/32768) // pPMC->PMC_PLLR = ((AT91C_CKGR_DIV & 0x05) | // (AT91C_CKGR_PLLCOUNT & (28<<8)) | // (AT91C_CKGR_MUL & (25<<16))); #define AT91_PMC_PLLR_INIT1 (AT91_PMC_CGMR_PLL_DIV(5) | \ AT91_PMC_CGMR_PLL_MUL(25) | \ AT91_PMC_CGMR_PLL_CNT(28)) #define AT91_PMC_MCKR_INIT2 (AT91_PMC_CSS_PLL_CLK | \ AT91_PMC_PRES_CLK_2) .macro _setup // set memory controller for internal flash, 0 WS up to 40 MHz, // 1 WS over 40 MHz // 48 MHz master clock frequency ldr r2,=AT91_BASE_MC ldr r3,=((48<<16)|AT91C_MC_FWS_1FWS) str r3,[r2,#AT91_MC_FMR] // Disable watchdog ldr r2, =AT91_BASE_WDTC ldr r3,=AT91C_SYSC_WDDIS str r3,[r2,#AT91_WDTC_WDMR] // Change system frequency from 32kHz to 24MHz (xtal 18.432 MHz). // First enable the master oscillator to run at 18.432MHz from // external crystal. ldr r2,=AT91_PMC ldr r3,=AT91_PMC_CGMR_INIT0 str r3,[r2,#AT91_PMC_MOR] // Wait for MOSC to stabilize. mov r4,#AT91_PMC_SR_MOSCS 1: ldr r3,[r2,#AT91_PMC_SR] and r3,r4,r3 cmp r3,r4 //#AT91_PMC_SR_MOSCS bne 1b // Now switch CPU clock to use master oscillator, after this we // should be running at 48MHz. ldr r3,=AT91_PMC_PLLR_INIT1 str r3,[r2,#AT91_PMC_PLLR] // Wait for PLL to stabilize mov r4,#AT91_PMC_SR_LOCK 2: ldr r3,[r2,#AT91_PMC_SR] and r3,r4,r3 cmp r3,r4 bne 2b // Now switch to PLL and divide with 2 ldr r3,=AT91_PMC_MCKR_INIT2 str r3,[r2,#AT91_PMC_MCKR] // All done, we should be running at 48MHz now 10: #if defined(CYG_HAL_STARTUP_ROMRAM) ldr r0,=0x01000000 // Relocate FLASH/ROM to on-chip RAM ldr r1,=0x02000000 // RAM base & length ldr r2,=0x02010000 20: ldr r3,[r0],#4 str r3,[r1],#4 cmp r1,r2 bne 20b ldr r0,=30f mov pc,r0 30: #endif _pclock_init _pio_init .endm #define CYGSEM_HAL_ROM_RESET_USES_JUMP #else // RAM start-up: .macro _setup // _led_init _pclock_init _pio_init .endm #endif #define PLATFORM_SETUP1 _setup //----------------------------------------------------------------------------- // end of hal_platform_setup.h #endif // CYGONCE_HAL_PLATFORM_SETUP_H