Re: [ECOS] NPE ethernet not working with Redboot v2.04

Re: [ECOS] NPE ethernet not working with Redboot v2.04

[Ravi R]

I see that the AHBQ Mgr registers are being byte swapped before being
written and are therefore being written wrong. Eg Q base address is
being written to where the read/write pointers should be in the
configuration word. This is being done by IX_OSAL_WRITE_LONG() based
on a flag IX_OSAL_LE_DC_MAPPING.

I have built Redboot in LE mode, using the Little Endian template, so
I assume all defines/byte swappings should be correct.
But obviously something is not right. Am not sure where the proper
place is to correct/set the defines.
There does not seem to be any setting in the ecos.ecc file.

The Xscale is correctly set to LE, the BYTE_SWAP_EN bit is set in the
EXPB CONTR. Am not sure if the MMU should/also cause the bytes to be
swapped when writting to the QMgr registers to compensate for the
IX_OS_WRITE_LONG() byte swap?

I would appreciate any help on what to set where...

FYI - Regarding the PHY - I stepped through the code pretty carefully
and it appears to correctly talk to the Phy - e.g it read the type of
Phy I am using LXT972 from a Phy register via the MII. (The board has
only one Phy)

RaviRe: NPE ethernet not working with Redboot v2.04
From: Mark Salter <msalter at redhat dot com>
To: Ravi R <rr94ca at gmail dot com>
Cc: ecos-discuss at ecos dot sourceware dot org
Date: Thu, 19 Jun 2008 09:04:57 -0400
Subject: Re: [ECOS] NPE ethernet not working with Redboot v2.04
References: <513ab1aa0806181926v6894d715ya04e1030d0b36025@mail.gmail.com>

>>On Wed, 2008-06-18 at 19:26 -0700, Ravi R wrote:
>> We are developing a product based on a board very similar to the Intel IXDP425.
>> We have taken the Redboot v2.04 source from the Intel IXP400 software
>> web site and built the source per instructions (with a few small
>> modifications to GPIO etc) and have installed Redboot on the board.
>> Redboot seems to be working fine including Serial, PCI configuration
>> and Flash services.
>> However, the Ethernet connection is not working.
>> A default ESA is set correctly, the NPE successfully detects and sets
>> up the PHY ("success using NPE-B with PHY 0"), the PHY link is
>> established (Link LED on PHY), the NPE subsystem seems to get
>> initialized correctly (no errors reported) and the NPE subsystem seems
>> to accept packets for transmission. However the NPE/Ethernet subsystem
>> does not appear to send out more than 1 packet (detected on the MII
>> TX_EN line to the Phy). All subsequent packets are blocked waiting on
>> the second packet to get transmitted (npe_can_send() returns 0). The
>> call sequence is as follows:

>Its hard to say what could be going wrong. Are you sure the first packet
>gets sent on the wire? Depending on how you have things configured, the
>"success using NPE-x with PHY n" message could have different meanings.
>If you have statically configured NPE-B to use PHY 0, then the message
>simply means that PHY 0 was found. It does not mean the PHY 0 is
>actually connected to NPE-B. All NPEs share the same mdc/mdio interface
>to the PHYs. So first, I would make sure that NPE-B really is connected
>to PHY 0.
>--Mark

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Re: [ECOS] NPE ethernet not working with Redboot v2.04

[Mark Salter]

On Fri, 2008-06-20 at 01:00 -0700, Ravi R wrote:
> I see that the AHBQ Mgr registers are being byte swapped before being
> written and are therefore being written wrong. Eg Q base address is
> being written to where the read/write pointers should be in the
> configuration word. This is being done by IX_OSAL_WRITE_LONG() based
> on a flag IX_OSAL_LE_DC_MAPPING.
> 
> I have built Redboot in LE mode, using the Little Endian template, so
> I assume all defines/byte swappings should be correct.
> But obviously something is not right. Am not sure where the proper
> place is to correct/set the defines.
> There does not seem to be any setting in the ecos.ecc file.
> 
> The Xscale is correctly set to LE, the BYTE_SWAP_EN bit is set in the
> EXPB CONTR. Am not sure if the MMU should/also cause the bytes to be
> swapped when writting to the QMgr registers to compensate for the
> IX_OS_WRITE_LONG() byte swap?

LE mode is just plain weird on the IXP4xx family. There are actually
two forms of LE (address coherent and data coherent). A bit in the
page table controls which form of LE is used for a given mapped area.

BE and LE have been thoroughly tested on the IXDP425 and other boards
so all the details of byte-swapping have already been worked out and
just setting CYGHWR_HAL_ARM_BIGENDIAN should be all that needs to be
done.

If at all possible, the initial debugging of RedBoot and the npe support
should be done in BE mode. That is the natural ordering and you won't
have to worry about the byte-swapping mess with LE mode.

In LE mode, the MMU has to provide two views of memory. If your memory
map has changed from the IXDP425, then you may have to change some of
the values in IxOsalOsIxp400.h to match those memory map changes. Also,
there was errata on some early versions of the IXP425 which did not
correctly handle LE mode. But if you're using a new board, I doubt that
is the problem.

> FYI - Regarding the PHY - I stepped through the code pretty carefully
> and it appears to correctly talk to the Phy - e.g it read the type of
> Phy I am using LXT972 from a Phy register via the MII. (The board has
> only one Phy)

All you need to read/write the PHY regs are mdc and mdio signals. That
doesn't mean that txclk/txdata/rxclk/rxdata/etc are correctly connected.

--Mark



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RE: [ECOS] NPE ethernet not working with Redboot v2.04

[Ravi R]

I tried your recommendation of testing the board in Big Endian.
The board works fine in Big Endian. All devices (UART, PCI, FLASH,
NPE/ETH) are recognized, setup, redboot boots up fine and I am able to
ping other hosts via the ethernet - NPE-B Phy 0.

In LE mode where the NPE/ETH does not work, It seems only the NPE/QMgr
component registers are being byte swapped and written incorrectly.
All other registers, EXPB, PCI, UART are written and work correctly.

With the CPU and debugger set in LE mode all the bit fields
constructed in CPU registers in preperation for writing to component
registers (UART, PCI, EXPB) match the bit field order defined in the
developer manual for these components. Since all of these are accessed
via the South AHB I expect the Bit field order for the QMGR registers
to be treated the same. So I do not understand the need to swap bytes
when writing to the QMGR registers, except when transferring ethernet
'data' that needs to be byte swapped. Even if the NPE reads the QMGR
registers in big endian, I would think the QMGR register bit field
definition is constant(?).

In anycase tried changing IXP_MAP_IO_DC to IXP_MAP_IO for
IXP425_QMGR_BASE in _platform_setup1, thinking that this ( the P bit
in the page table) may reverse the effect of the IX_OSAL_WRITE_LONG()
byte swap just for the QMGR component, but this did not seem to have
any effect.

I also tried forcing IX_OSAL_WRITE_LONG() to not do byte swapping by
removing the IX_COMPONENT_NAME definition in
IxOsalOsalIxp400CustomizedMappings.h to define IX_OSAL_LE_AC_MAPPING
instead of IX_OSAL_LE_DC_MAPPING.
This seems to write the QMgr registers with values that makes sense
but also causes other problems that I was not able
to track down/resolve.

Given that the Redboot code V2.04 has been thoroughly tested in LE and
BE mode and all byte swapping should be
dealt with by setting CYGHWR_HAL_ARM_BIGENDIAN I am at a loss as to
how to explain what I am seeing.

Our memory map has not changed from the IXDP425 - our board has a few
less devices and smaller RAM.

I must be doing something wrong/mis understanding something.
Any guidance would be appreciated.
Ravi

>
> LE mode is just plain weird on the IXP4xx family. There are
> actually two forms of LE (address coherent and data
> coherent). A bit in the page table controls which form of LE
> is used for a given mapped area.
>
> BE and LE have been thoroughly tested on the IXDP425 and
> other boards so all the details of byte-swapping have already
> been worked out and just setting CYGHWR_HAL_ARM_BIGENDIAN
> should be all that needs to be done.
>
> If at all possible, the initial debugging of RedBoot and the
> npe support should be done in BE mode. That is the natural
> ordering and you won't have to worry about the byte-swapping
> mess with LE mode.
>
> In LE mode, the MMU has to provide two views of memory. If
> your memory map has changed from the IXDP425, then you may
> have to change some of the values in IxOsalOsIxp400.h to
> match those memory map changes. Also, there was errata on
> some early versions of the IXP425 which did not correctly
> handle LE mode. But if you're using a new board, I doubt that
> is the problem.
>
> All you need to read/write the PHY regs are mdc and mdio
> signals. That doesn't mean that txclk/txdata/rxclk/rxdata/etc
> are correctly connected.
>
> --Mark

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Re: [ECOS] NPE ethernet not working with Redboot v2.04

[Mark Salter]

On Wed, 2008-06-18 at 19:26 -0700, Ravi R wrote:
> We are developing a product based on a board very similar to the Intel IXDP425.
> We have taken the Redboot v2.04 source from the Intel IXP400 software
> web site and built the source per instructions (with a few small
> modifications to GPIO etc) and have installed Redboot on the board.
> Redboot seems to be working fine including Serial, PCI configuration
> and Flash services.
> However, the Ethernet connection is not working.
> A default ESA is set correctly, the NPE successfully detects and sets
> up the PHY ("success using NPE-B with PHY 0"), the PHY link is
> established (Link LED on PHY), the NPE subsystem seems to get
> initialized correctly (no errors reported) and the NPE subsystem seems
> to accept packets for transmission. However the NPE/Ethernet subsystem
> does not appear to send out more than 1 packet (detected on the MII
> TX_EN line to the Phy). All subsequent packets are blocked waiting on
> the second packet to get transmitted (npe_can_send() returns 0). The
> call sequence is as follows:

Its hard to say what could be going wrong. Are you sure the first packet
gets sent on the wire? Depending on how you have things configured, the
"success using NPE-x with PHY n" message could have different meanings.
If you have statically configured NPE-B to use PHY 0, then the message
simply means that PHY 0 was found. It does not mean the PHY 0 is
actually connected to NPE-B. All NPEs share the same mdc/mdio interface
to the PHYs. So first, I would make sure that NPE-B really is connected
to PHY 0.

--Mark



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[ECOS] NPE ethernet not working with Redboot v2.04

[Ravi R]

We are developing a product based on a board very similar to the Intel IXDP425.
We have taken the Redboot v2.04 source from the Intel IXP400 software
web site and built the source per instructions (with a few small
modifications to GPIO etc) and have installed Redboot on the board.
Redboot seems to be working fine including Serial, PCI configuration
and Flash services.
However, the Ethernet connection is not working.
A default ESA is set correctly, the NPE successfully detects and sets
up the PHY ("success using NPE-B with PHY 0"), the PHY link is
established (Link LED on PHY), the NPE subsystem seems to get
initialized correctly (no errors reported) and the NPE subsystem seems
to accept packets for transmission. However the NPE/Ethernet subsystem
does not appear to send out more than 1 packet (detected on the MII
TX_EN line to the Phy). All subsequent packets are blocked waiting on
the second packet to get transmitted (npe_can_send() returns 0). The
call sequence is as follows:

..
npe_init()
npe_csr_load()
 ...
npe_start()

1st packet:
npe_can_send(): true
npe_send()
 packet passed to NPE subsystem - MII sees packet

2nd packet
npe_can_send() : true
npe_send()
 packet passed to NPE subsystem - MII does not see packet

3rd Packet
npe_can_send() : 0
npe_can_send() : 0
npe_can_send() : 0
..

A polling function npe_poll() seems to get called after the npe_send -
which I assume should service the Ethernet MAC in someway - for tx
done callback (?) ..
Am digging into the NPE code to understand it, but any help on what to
look for would be appreciated.
Ravi

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