/*========================================================================== // // at91_misc.c // // HAL misc board support code for Atmel AT91 // //========================================================================== //####ECOSGPLCOPYRIGHTBEGIN#### // ------------------------------------------- // This file is part of eCos, the Embedded Configurable Operating System. // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. // Copyright (C) 2003 Nick Garnett // // eCos is free software; you can redistribute it and/or modify it under // the terms of the GNU General Public License as published by the Free // Software Foundation; either version 2 or (at your option) any later version. // // eCos is distributed in the hope that it will be useful, but WITHOUT ANY // WARRANTY; without even the implied warranty of MERCHANTABILITY or // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License // for more details. // // You should have received a copy of the GNU General Public License along // with eCos; if not, write to the Free Software Foundation, Inc., // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. // // As a special exception, if other files instantiate templates or use macros // or inline functions from this file, or you compile this file and link it // with other works to produce a work based on this file, this file does not // by itself cause the resulting work to be covered by the GNU General Public // License. However the source code for this file must still be made available // in accordance with section (3) of the GNU General Public License. // // This exception does not invalidate any other reasons why a work based on // this file might be covered by the GNU General Public License. // // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. // at http://sources.redhat.com/ecos/ecos-license/ // ------------------------------------------- //####ECOSGPLCOPYRIGHTEND#### //========================================================================== //#####DESCRIPTIONBEGIN#### // // Author(s): gthomas // Contributors: gthomas, jskov, nickg, tkoeller, jjung, jbork // Date: 2001-07-12 // Purpose: HAL board support // Description: Implementations of HAL board interfaces // Modification: Modified according to Sensitron example to fit current CVS version. All changes are shown inside // Begin/End Antenna2k4 changes // //####DESCRIPTIONEND#### // //========================================================================*/ #include #include // base types #include // tracing macros #include // assertion macros #include // IO macros #include // Register state info #include #include // necessary? #include #include // calling interface #include // helper functions #ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT #include // HAL ISR support #endif #include // platform registers // Begin Antenna2k4 changes #include // platform registers // End Antenna2k4 changes // ------------------------------------------------------------------------- // Clock support static cyg_uint32 _period; void hal_clock_initialize(cyg_uint32 period) { CYG_ADDRESS timer = AT91_TC+AT91_TC_TC0; // Begin Antenna2k4 changes cyg_uint32 ps_clock_register; // Enable Timer Counter 0 in Power Save clock enable register HAL_READ_UINT32(AT91_PS+AT91_PS_PCSR, ps_clock_register); ps_clock_register &= (AT91_PS_PCER_PIO | AT91_PS_PCER_US0 | AT91_PS_PCER_US1); ps_clock_register |= AT91_PS_PCER_TC0; HAL_WRITE_UINT32(AT91_PS+AT91_PS_PCER, ps_clock_register); // End Antenna2k4 changes CYG_ASSERT(period < 0x10000, "Invalid clock period"); // Disable counter HAL_WRITE_UINT32(timer+AT91_TC_CCR, AT91_TC_CCR_CLKDIS); // Set registers HAL_WRITE_UINT32(timer+AT91_TC_CMR, AT91_TC_CMR_CPCTRG | // Reset counter on CPC AT91_TC_CMR_CLKS_MCK32); // 1 MHz HAL_WRITE_UINT32(timer+AT91_TC_RC, period); // Start timer HAL_WRITE_UINT32(timer+AT91_TC_CCR, AT91_TC_CCR_TRIG | AT91_TC_CCR_CLKEN); // Enable timer 0 interrupt HAL_WRITE_UINT32(timer+AT91_TC_IER, AT91_TC_IER_CPC); } void hal_clock_reset(cyg_uint32 vector, cyg_uint32 period) { CYG_ADDRESS timer = AT91_TC+AT91_TC_TC0; cyg_uint32 sr; CYG_ASSERT(period < 0x10000, "Invalid clock period"); HAL_READ_UINT32(timer+AT91_TC_SR, sr); // Clear interrupt // Begin Antenna2k4 changes HAL_INTERRUPT_ACKNOWLEDGE(CYGNUM_HAL_INTERRUPT_RTC); // End Antenna2k4 changes if (period != _period) { hal_clock_initialize(period); } _period = period; } void hal_clock_read(cyg_uint32 *pvalue) { CYG_ADDRESS timer = AT91_TC+AT91_TC_TC0; cyg_uint32 val; HAL_READ_UINT32(timer+AT91_TC_CV, val); *pvalue = val; } // ------------------------------------------------------------------------- // // Delay for some number of micro-seconds // Use timer #2 in MCLOCK/32 mode. // void hal_delay_us(cyg_int32 usecs) { CYG_ADDRESS timer = AT91_TC+AT91_TC_TC2; cyg_uint32 stat; cyg_uint64 ticks; // Calculate how many timer ticks the required number of // microseconds equate to. We do this calculation in 64 bit // arithmetic to avoid overflow. ticks = (((cyg_uint64)usecs) * ((cyg_uint64)CYGNUM_HAL_ARM_AT91_CLOCK_SPEED))/32000000LL; // Disable counter HAL_WRITE_UINT32(timer+AT91_TC_CCR, AT91_TC_CCR_CLKDIS); // Set registers HAL_WRITE_UINT32(timer+AT91_TC_CMR, AT91_TC_CMR_CLKS_MCK32); // 1MHz HAL_WRITE_UINT32(timer+AT91_TC_RA, 0); HAL_WRITE_UINT32(timer+AT91_TC_RC, ticks); // Start timer HAL_WRITE_UINT32(timer+AT91_TC_CCR, AT91_TC_CCR_TRIG | AT91_TC_CCR_CLKEN); // Wait for the compare do { HAL_READ_UINT32(timer+AT91_TC_SR, stat); } while ((stat & AT91_TC_SR_CPC) == 0); } // ------------------------------------------------------------------------- // Hardware init void hal_hardware_init(void) { unsigned i; // Set up eCos/ROM interfaces hal_if_init(); // Reset all interrupts HAL_WRITE_UINT32(AT91_AIC+AT91_AIC_IDCR, 0xFFFFFFFF); // Flush internal priority level stack for (i = 0; i < 8; ++i) HAL_WRITE_UINT32(AT91_AIC+AT91_AIC_EOI, 0xFFFFFFFF); } // ------------------------------------------------------------------------- // This routine is called to respond to a hardware interrupt (IRQ). It // should interrogate the hardware and return the IRQ vector number. // Begin Antenna2k4 changes /* int hal_IRQ_handler(void) { cyg_uint32 irq_num; cyg_uint32 ivr; // Calculate active interrupt (updates ISR) HAL_READ_UINT32(AT91_AIC+AT91_AIC_IVR, ivr); HAL_READ_UINT32(AT91_AIC+AT91_AIC_ISR, irq_num); // No valid interrrupt source, treat as spurious interrupt if (irq_num < CYGNUM_HAL_ISR_MIN || irq_num > CYGNUM_HAL_ISR_MAX) irq_num = CYGNUM_HAL_INTERRUPT_NONE; return irq_num; } */ int hal_IRQ_handler(void) { cyg_uint32 irq_num; cyg_uint32 ipr, imr; HAL_READ_UINT32(AT91_AIC+AT91_AIC_IPR, ipr); HAL_READ_UINT32(AT91_AIC+AT91_AIC_IMR, imr); ipr &= imr; for (irq_num = 0; irq_num < 19; irq_num++) { if (ipr & (1 << irq_num)) { break; } } return irq_num; } // End Antenna2k4 changes // ------------------------------------------------------------------------- // Interrupt control // void hal_interrupt_mask(int vector) { CYG_ASSERT(vector <= CYGNUM_HAL_ISR_MAX && vector >= CYGNUM_HAL_ISR_MIN , "Invalid vector"); HAL_WRITE_UINT32(AT91_AIC+AT91_AIC_IDCR, (1<= CYGNUM_HAL_ISR_MIN , "Invalid vector"); HAL_WRITE_UINT32(AT91_AIC+AT91_AIC_IECR, (1<= CYGNUM_HAL_ISR_MIN , "Invalid vector"); HAL_WRITE_UINT32(AT91_AIC+AT91_AIC_ICCR, (1<= CYGNUM_HAL_ISR_MIN , "Invalid vector"); if (level) { if (up) { mode = AT91_AIC_SMR_LEVEL_HI; } else { mode = AT91_AIC_SMR_LEVEL_LOW; } } else { if (up) { mode = AT91_AIC_SMR_EDGE_POS; } else { mode = AT91_AIC_SMR_EDGE_NEG; } } mode |= 7; // Default priority HAL_WRITE_UINT32(AT91_AIC+(AT91_AIC_SMR0+(vector*4)), mode); } void hal_interrupt_set_level(int vector, int level) { cyg_uint32 mode; CYG_ASSERT(vector <= CYGNUM_HAL_ISR_MAX && vector >= CYGNUM_HAL_ISR_MIN , "Invalid vector"); CYG_ASSERT(level >= 0 && level <= 7, "Invalid level"); HAL_READ_UINT32(AT91_AIC+(AT91_AIC_SMR0+(vector*4)), mode); mode = (mode & ~AT91_AIC_SMR_PRIORITY) | level; HAL_WRITE_UINT32(AT91_AIC+(AT91_AIC_SMR0+(vector*4)), mode); } void hal_show_IRQ(int vector, int data, int handler) { // UNDEFINED(__FUNCTION__); // FIXME } // Begin Antenna2k4 changes // // Diagnostic LEDs - there are three colored LEDs which can be used // to send a simple diagnostic value (8 bits) // void _at91_led(int val) { int i, to; HAL_WRITE_UINT32(AT91_PIO+AT91_PIO_CODR, 0x06); // DATA+CLOCK LEDs off for (to = 0; to < 0x200000; to++) ; for (i = 0; i < 8; i++) { HAL_WRITE_UINT32(AT91_PIO+AT91_PIO_SODR, ((val>>(7-i)) & 0x01)<<2); // DATA LED HAL_WRITE_UINT32(AT91_PIO+AT91_PIO_SODR, 0x02); // CLOCK LED on for (to = 0; to < 0x80000; to++) ; HAL_WRITE_UINT32(AT91_PIO+AT91_PIO_CODR, 0x02); // CLOCK LED off for (to = 0; to < 0x40000; to++) ; HAL_WRITE_UINT32(AT91_PIO+AT91_PIO_CODR, 0x04); // DATA LED off } } void set_leds(int val) { HAL_WRITE_UINT32(AT91_PIO+AT91_PIO_CODR, 0x16); HAL_WRITE_UINT32(AT91_PIO+AT91_PIO_SODR, val); } // End Antenna2k4 changes /* Use the watchdog to generate a reset */ void hal_at91_reset_cpu(void) { HAL_WRITE_UINT32(AT91_WD + AT91_WD_OMR, AT91_WD_OMR_OKEY); HAL_WRITE_UINT32(AT91_WD + AT91_WD_CMR, AT91_WD_CMR_CKEY); HAL_WRITE_UINT32(AT91_WD + AT91_WD_CR, AT91_WD_CR_RSTKEY); HAL_WRITE_UINT32(AT91_WD + AT91_WD_OMR, AT91_WD_OMR_OKEY | AT91_WD_OMR_RSTEN | AT91_WD_OMR_WDEN); while(1) CYG_EMPTY_STATEMENT; } //-------------------------------------------------------------------------- // EOF at91_misc.c