#ifndef CYGONCE_HAL_PLF_IO_H #define CYGONCE_HAL_PLF_IO_H //============================================================================= // // plf_io.h // // EB40A board specific registers // //============================================================================= //####ECOSGPLCOPYRIGHTBEGIN#### // ------------------------------------------- // This file is part of eCos, the Embedded Configurable Operating System. // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. // // eCos is free software; you can redistribute it and/or modify it under // the terms of the GNU General Public License as published by the Free // Software Foundation; either version 2 or (at your option) any later version. // // eCos is distributed in the hope that it will be useful, but WITHOUT ANY // WARRANTY; without even the implied warranty of MERCHANTABILITY or // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License // for more details. // // You should have received a copy of the GNU General Public License along // with eCos; if not, write to the Free Software Foundation, Inc., // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. // // As a special exception, if other files instantiate templates or use macros // or inline functions from this file, or you compile this file and link it // with other works to produce a work based on this file, this file does not // by itself cause the resulting work to be covered by the GNU General Public // License. However the source code for this file must still be made available // in accordance with section (3) of the GNU General Public License. // // This exception does not invalidate any other reasons why a work based on // this file might be covered by the GNU General Public License. // // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. // at http://sources.redhat.com/ecos/ecos-license/ // ------------------------------------------- //####ECOSGPLCOPYRIGHTEND#### //============================================================================= //#####DESCRIPTIONBEGIN#### // // Author(s): tkoeller // Contributors: tdrury, jjung, jbork // Date: 2002-06-22 // Purpose: Atmel EB40A board specific registers // Description: // Modification: Modified according to Sensitron example to fit current CVS // version. All changes are shown inside // Begin/End Antenna2k4 changes // Usage: #include // //####DESCRIPTIONEND#### // //============================================================================= // these io pins are for the LEDs. #define EB40A_LED1 0x00000008 #define EB40A_LED2 0x00000010 #define EB40A_LED3 0x00000020 #define EB40A_LED4 0x00000040 // these PIOs double as TCLK1, TIOA1, TIOB1, TCLK2 respectively. #define EB40A_LED5 0x00010000 #define EB40A_LED6 0x00020000 #define EB40A_LED7 0x00040000 #define EB40A_LED8 0x00080000 #define EB40A_LED_ALL 0x00f00078 // Push buttons. Note that these are connected to interrupt lines. #define EB40A_SW1 0x00001000 #define EB40A_SW2 0x00000100 #define EB40A_SW3 0x00000002 #define EB40A_SW4 0x00000004 // Push buttons. Note that these are connected to interrupt lines. #define EB40A_SW1 0x00001000 #define EB40A_SW2 0x00000100 #define EB40A_SW3 0x00000002 #define EB40A_SW4 0x00000004 // Begin Antenna2k4 changes #define AT91_PS_PCER_PIO 0x100 // Parallel I/O clock #define AT91_PS_PCER_TC2 0x040 // Timer Counter 2 clock #define AT91_PS_PCER_TC1 0x020 // Timer Counter 1 clock #define AT91_PS_PCER_TC0 0x010 // Timer Counter 0 clock #define AT91_PS_PCER_US1 0x008 // USART 1 clock #define AT91_PS_PCER_US0 0x004 // USART 0 clock // Waveform mode definitions #define AT91_TC_CMRWF_CLKS 0 #define AT91_TC_CMRWF_CLKS_MCK2 (0<<0) #define AT91_TC_CMRWF_CLKS_MCK8 (1<<0) #define AT91_TC_CMRWF_CLKS_MCK32 (2<<0) #define AT91_TC_CMRWF_CLKS_MCK128 (3<<0) #define AT91_TC_CMRWF_CLKS_MCK1024 (4<<0) #define AT91_TC_CMRWF_CLKS_XC0 (5<<0) #define AT91_TC_CMRWF_CLKS_XC1 (6<<0) #define AT91_TC_CMRWF_CLKS_XC2 (7<<0) #define AT91_TC_CMRWF_CLKI (1<<3) #define AT91_TC_CMFWF_BURST_NONE (0<<4) #define AT91_TC_CMFWF_BURST_XC0 (1<<4) #define AT91_TC_CMFWF_BURST_XC1 (2<<4) #define AT91_TC_CMFWF_BURST_XC2 (3<<4) #define AT91_TC_CMRWF_CPCSTOP (1<<6) #define AT91_TC_CMRWF_CPCDIS (1<<7) #define AT91_TC_CMRWF_EEVTEDG_NONE (0<<8) #define AT91_TC_CMRWF_EEVTEDG_RISE (1<<8) #define AT91_TC_CMRWF_EEVTEDG_FALL (2<<8) #define AT91_TC_CMRWF_EEVTEDG_BOTH (3<<8) #define AT91_TC_CMRWF_EEVT_TIOB (0<<10) #define AT91_TC_CMRWF_EEVT_XC0 (1<<10) #define AT91_TC_CMRWF_EEVT_XC1 (2<<10) #define AT91_TC_CMRWF_EEVT_XC2 (3<<10) #define AT91_TC_CMRWF_ENETRG (1<<12) #define AT91_TC_CMRWF_CPCTRG (1<<14) #define AT91_TC_CMRWF_WAVE (1<<15) #define AT91_TC_CMRWF_ACPA_NONE (0<<16) #define AT91_TC_CMRWF_ACPA_SET (1<<16) #define AT91_TC_CMRWF_ACPA_CLEAR (2<<16) #define AT91_TC_CMRWF_ACPA_TOGGLE (3<<16) #define AT91_TC_CMRWF_ACPC_NONE (0<<18) #define AT91_TC_CMRWF_ACPC_SET (1<<18) #define AT91_TC_CMRWF_ACPC_CLEAR (2<<18) #define AT91_TC_CMRWF_ACPC_TOGGLE (3<<18) #define AT91_TC_CMRWF_AEEVT_NONE (0<<20) #define AT91_TC_CMRWF_AEEVT_SET (1<<20) #define AT91_TC_CMRWF_AEEVT_CLEAR (2<<20) #define AT91_TC_CMRWF_AEEVT_TOGGLE (3<<20) #define AT91_TC_CMRWF_ASWTRG_NONE (0<<20) #define AT91_TC_CMRWF_ASWTRG_SET (1<<20) #define AT91_TC_CMRWF_ASWTRG_CLEAR (2<<20) #define AT91_TC_CMRWF_ASWTRG_TOGGLE (3<<20) #define AT91_TC_CMRWF_BCPB_NONE (0<<24) #define AT91_TC_CMRWF_BCPB_SET (1<<24) #define AT91_TC_CMRWF_BCPB_CLEAR (2<<24) #define AT91_TC_CMRWF_BCPB_TOGGLE (3<<24) #define AT91_TC_CMRWF_BCPC_NONE (0<<26) #define AT91_TC_CMRWF_BCPC_SET (1<<26) #define AT91_TC_CMRWF_BCPC_CLEAR (2<<26) #define AT91_TC_CMRWF_BCPC_TOGGLE (3<<26) #define AT91_TC_CMRWF_BEEVT_NONE (0<<28) #define AT91_TC_CMRWF_BEEVT_SET (1<<28) #define AT91_TC_CMRWF_BEEVT_CLEAR (2<<28) #define AT91_TC_CMRWF_BEEVT_TOGGLE (3<<28) #define AT91_TC_CMRWF_BSWTRG_NONE (0<<30) #define AT91_TC_CMRWF_BSWTRG_SET (1<<30) #define AT91_TC_CMRWF_BSWTRG_CLEAR (2<<30) #define AT91_TC_CMRWF_BSWTRG_TOGGLE (3<<30) // End Antenna2k4 changes //----------------------------------------------------------------------------- // end of plf_io.h #endif // CYGONCE_HAL_PLF_IO_H