[ECOS] problems with rltk8139 driver

[ECOS] problems with rltk8139 driver

[jerzy dyrda]

Hi all,
I've a custom board based on XScale IXP425. I'm in the process of porting 
rltk8139 driver on this board. Sending data are ok ( I use ethereal to 
check), but  receive fail. In receive buffer (rltk8139_eth0_rx_ring) miss a 
few data -about first 20 bytes. In this data should be a receive packet 
header, because it is zero driver doesn't receive more. Rltk8139_eth0_rx_ring 
is allocated in cached memory but all reading are done by uncached memory 
(MMU translate address). I  check up on either memory region - it's the same. 
I think this is not a  problem of memory coherency ( I use 
HAL_DCACHE_INVALIDATE macro and result is the same). It seems to me that chip 
doesn't copy all datas. 

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Re: [ECOS] problems with rltk8139 driver

[Andrew Lunn]

On Mon, Aug 23, 2004 at 04:41:46PM +0200, jerzy dyrda wrote:
> Hi all,

> I've a custom board based on XScale IXP425. I'm in the process of
> porting rltk8139 driver on this board. Sending data are ok ( I use
> ethereal to check), but receive fail. In receive buffer
> (rltk8139_eth0_rx_ring) miss a few data -about first 20 bytes. In
> this data should be a receive packet header, because it is zero
> driver doesn't receive more. Rltk8139_eth0_rx_ring is allocated in
> cached memory but all reading are done by uncached memory (MMU
> translate address). I check up on either memory region - it's the
> same.  I think this is not a problem of memory coherency ( I use
> HAL_DCACHE_INVALIDATE macro and result is the same). It seems to me
> that chip doesn't copy all datas.

It seems strange it does not copy the beginning of the packet. I would
read the data sheet about DMA. Is any specific alligment needed? eg on
8 / 16 / 32 byte boundaries? Also take a look backwards. See if the
whole packet is there but offset by 20 bytes. This seems unlikely
because this would probably corrupt the data structures and you would
get a crash. 

You say the memory is allocated in cached memory. Check what values
are programmed into the ethernet chip. Cached or none cached. 

        Andrew

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