[ECOS] Cortex M3 architecture

[ECOS] Cortex M3 architecture

[simon.kallweit]

Hello everyone

I'm planning on starting an initial effort to port eCos to the Cortex M3 
architecture, using the STM3210E-EVAL board as the initial target. After 
studying the current ARM architecture code, as well as some of it's 
variants and platforms, I wonder if the Cortex M3 should be implemented 
as a variant of the ARM architecture, or as a complete new architecture 
of it's own. I think I'd prefer to start a new architecture, as the M3 
differs quite a bit from the normal ARM architecture in terms of context 
switching as well as interrupt and exception handing. Also the M3 
exclusively runs Thumb2 instructions, so all the current assembler code 
using normal ARM instructions cannot be used. I think writing a new 
architecture saves us from introducing quite a mess in the current ARM 
architecture code. What do you think?

I wonder if the other Cortex variants (A8, A9, R4, M1) should be 
considered for porting from the beginning. My focus is clearly on the 
M3, but if anyone is willing to work on the other variants this should 
be considered now.

Also if anyone is interested to help, please inform me.

Best regards,
Simon

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Re: [ECOS] Cortex M3 architecture

[Andrew Lunn]

> I wonder if the other Cortex variants (A8, A9, R4, M1) should be  
> considered for porting from the beginning. My focus is clearly on the  
> M3, but if anyone is willing to work on the other variants this should  
> be considered now.

Have you seen any documents which compares/contrasts the different
Cortex variants. Before answering your question it is necessary to
know how similar/different the different variants are.

     Andrew

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Re: [ECOS] Cortex M3 architecture

[simon.kallweit]

Andrew Lunn wrote:
>> I wonder if the other Cortex variants (A8, A9, R4, M1) should be  
>> considered for porting from the beginning. My focus is clearly on the  
>> M3, but if anyone is willing to work on the other variants this should  
>> be considered now.
>>     
>
> Have you seen any documents which compares/contrasts the different
> Cortex variants. Before answering your question it is necessary to
> know how similar/different the different variants are.
>   

No I haven't really. All I know is that the variants all have very 
different application profiles. A series being mostly for complex OS and 
applications, R series for more complex embedded applications and the M 
series for deeply embedded applications. A & R also support normal Thumb 
and ARM instructions. Perhaps someone else can give some insight?

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Re: [ECOS] Cortex M3 architecture

[Andrew Lunn]

> No I haven't really. All I know is that the variants all have very  
> different application profiles. A series being mostly for complex OS and  
> applications, R series for more complex embedded applications and the M  
> series for deeply embedded applications. A & R also support normal Thumb  
> and ARM instructions. Perhaps someone else can give some insight?

I was just skimming through the ARM website. 

The M1 and M3 only supports thumb2. They have a complete different
interrupt controller, the NVIC. They only have two operating modes,
unlike the old processors which has 7 modes. I could not find much
documentation about the M1. It is designed to be used on FPGA, so i
guess you can synthesis it. That probably means you can leave bits of
it out, extend it etc. However it looks like it supports the NVIC as
well. The NVIC also gives you your system tick, which is nice.

I would agree that a new architecture port is the way to go. The
Cortex M? is just too different. I also think you can safely ignore
the A and R processors. However i think you should try to include both
M1 and M3 in your architecture package, if possible.

   Andrew


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[ECOS] Re: Cortex M3 architecture

[Grant Edwards]

On 2008-09-01, simon.kallweit@intefo.ch <simon.kallweit@intefo.ch> wrote:
> Andrew Lunn wrote:
>>> I wonder if the other Cortex variants (A8, A9, R4, M1) should
>>> be considered for porting from the beginning. My focus is
>>> clearly on the M3, but if anyone is willing to work on the
>>> other variants this should be considered now.
>>
>> Have you seen any documents which compares/contrasts the
>> different Cortex variants. Before answering your question it
>> is necessary to know how similar/different the different
>> variants are.
>
> No I haven't really. All I know is that the variants all have
> very different application profiles. A series being mostly for
> complex OS and applications, R series for more complex
> embedded applications and the M series for deeply embedded
> applications. A & R also support normal Thumb and ARM
> instructions. Perhaps someone else can give some insight?

I would think that Thumb2 processors like the M3 would need to
be a different architecture than ARM.  It's a different
instruction set -- isn't that what defines an architecture?
Whether the A and R series would fit best under an ARM
architecture or a Thumb2 architecture, I won't hazard a guess
(I've only studied the M3).

-- 
Grant




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Re: [ECOS] Re: Cortex M3 architecture

[Andrew Lunn]

> I would think that Thumb2 processors like the M3 would need to
> be a different architecture than ARM.  It's a different
> instruction set -- isn't that what defines an architecture?

With ARM it is all a bit messy. eg some of the processors support
thumb2 as an add on, just like the support thumb. For such processors,
you could add thumb2 support to the existing ARM architecture, with
the understanding that all interrupt handling is done in the good old
ARM instruction set. However user code could be in thumb/thumb2.

For the Cortex M processors you cannot do this, so a new architecture
is needed when you _only_ have thumb/thumb2. 

   Andrew

    

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Re: [ECOS] Re: Cortex M3 architecture

[Simon Kallweit]

Andrew Lunn schrieb:
>> I would think that Thumb2 processors like the M3 would need to
>> be a different architecture than ARM.  It's a different
>> instruction set -- isn't that what defines an architecture?
>>     
>
> With ARM it is all a bit messy. eg some of the processors support
> thumb2 as an add on, just like the support thumb. For such processors,
> you could add thumb2 support to the existing ARM architecture, with
> the understanding that all interrupt handling is done in the good old
> ARM instruction set. However user code could be in thumb/thumb2.
>
> For the Cortex M processors you cannot do this, so a new architecture
> is needed when you _only_ have thumb/thumb2. 
>
>   
So, I guess we should introduce a new architecture named "armv7m". I 
think this makes sense as we can then support both M3 and M1 as 
variants. What do you think?

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Re: [ECOS] Re: Cortex M3 architecture

[Simon Kallweit]

Simon Kallweit schrieb:
> Andrew Lunn schrieb:
>>> I would think that Thumb2 processors like the M3 would need to
>>> be a different architecture than ARM.  It's a different
>>> instruction set -- isn't that what defines an architecture?
>>>     
>>
>> With ARM it is all a bit messy. eg some of the processors support
>> thumb2 as an add on, just like the support thumb. For such processors,
>> you could add thumb2 support to the existing ARM architecture, with
>> the understanding that all interrupt handling is done in the good old
>> ARM instruction set. However user code could be in thumb/thumb2.
>>
>> For the Cortex M processors you cannot do this, so a new architecture
>> is needed when you _only_ have thumb/thumb2.
>>   
> So, I guess we should introduce a new architecture named "armv7m". I 
> think this makes sense as we can then support both M3 and M1 as 
> variants. What do you think?
>

I still wonder what we should use as the architecture name. "armv7m" is 
obviously wrong, as the M1 is actually an armv6m. So, should the new 
architecture be named "cortex", or maybe "cortexm"? Any ideas are very 
welcome.

Simon

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Re: [ECOS] Re: Cortex M3 architecture

[Robin Randhawa]

Hey Simon.

On Tue, 2008-09-02 at 13:33 +0200, Simon Kallweit wrote:

> I still wonder what we should use as the architecture name. "armv7m" is 
> obviously wrong, as the M1 is actually an armv6m.

I agree that any allusion to v7 isn't a good idea.

>  So, should the new 
> architecture be named "cortex", or maybe "cortexm"? Any ideas are very 
> welcome.

M1 and M3 appear to be intrinsically the same. I suppose cortex-m would
be fine. People could do variant ports as needed.

Out of curiosity, what eval board are you using for your port ?
I have access to a LM3S6965EVB from Luminary and could chip in the
porting process.

Cheers,
Robin


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Re: [ECOS] Re: Cortex M3 architecture

[simon.kallweit]

Robin Randhawa wrote:
> Hey Simon.
>
> On Tue, 2008-09-02 at 13:33 +0200, Simon Kallweit wrote:
>
>   
>> I still wonder what we should use as the architecture name. "armv7m" is 
>> obviously wrong, as the M1 is actually an armv6m.
>>     
>
> I agree that any allusion to v7 isn't a good idea.
>
>   
>>  So, should the new 
>> architecture be named "cortex", or maybe "cortexm"? Any ideas are very 
>> welcome.
>>     
>
> M1 and M3 appear to be intrinsically the same. I suppose cortex-m would
> be fine. People could do variant ports as needed.
>   

I'm currently using "cortexm" as the architecture name. May be changed 
later on if necessary. The port will be a very iterative process anyway.

> Out of curiosity, what eval board are you using for your port ?
> I have access to a LM3S6965EVB from Luminary and could chip in the
> porting process.
>   

I'm currently using an STMicroelectronics STM3210E-EVAL board with an 
STM32F103ZET6 controller. Would be great to see support for Luminary 
processors early on, as this would help get the architecture, variant, 
platform layering right from the beginning.


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Re: [ECOS] Re: Cortex M3 architecture

[Robin Randhawa]

On Wed, 2008-09-03 at 09:27 +0200, simon.kallweit@intefo.ch wrote:

> I'm currently using an STMicroelectronics STM3210E-EVAL board with an 
> STM32F103ZET6 controller. Would be great to see support for Luminary 
> processors early on, as this would help get the architecture, variant, 
> platform layering right from the beginning.

Agreed. Are you in a position to collaborate on the porting effort at
all ? I'd much rather avoid redundancy if possible. I've been looking at
eCos for a different project [MIPS Alchemy based board] which just got
shelved so am idling for the moment.

Cheers,
Robin




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Re: [ECOS] Re: Cortex M3 architecture

[Andrew Lunn]

Hi Folks

As an eCos maintainer it is great to see people interested in a new
architecture port and it looks like people will be working together to
achieve this.

One thing i should stress now, before things get going, code is
written and patches start flying around, is that in order to get the
finished code into the eCos repository you need to ensure that all
contributors have copyright assignments with the FSF. 

Getting such copyright assignments can be a long slow process. So
don't let it stop development. However you need to keep track of who
contributed what so at the end of the development work, you can show
who has developed it and that they all have copyright assignments.

    Andrew

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Re: [ECOS] Re: Cortex M3 architecture

[simon.kallweit]

Robin Randhawa wrote:
> On Wed, 2008-09-03 at 09:27 +0200, simon.kallweit@intefo.ch wrote:
>
>   
>> I'm currently using an STMicroelectronics STM3210E-EVAL board with an 
>> STM32F103ZET6 controller. Would be great to see support for Luminary 
>> processors early on, as this would help get the architecture, variant, 
>> platform layering right from the beginning.
>>     
>
> Agreed. Are you in a position to collaborate on the porting effort at
> all ? I'd much rather avoid redundancy if possible. I've been looking at
> eCos for a different project [MIPS Alchemy based board] which just got
> shelved so am idling for the moment.
>   

It's not yet decided, but it seems that my company will use eCos in 
upcoming projects. As these designs are based on STM32 processors, we 
would like to invest in the eCos architecture port. So as it seems, I'll 
get payed time to do the port, and yes, I'm really looking forward to 
collaborate with others. If my company makes the decision in favor of 
eCos, I'll start working right away.

How much time can you spend, working on the port?


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Re: [ECOS] Re: Cortex M3 architecture

[simon.kallweit]

Andrew Lunn wrote:
> Hi Folks
>
> As an eCos maintainer it is great to see people interested in a new
> architecture port and it looks like people will be working together to
> achieve this.
>   

I hope so :)
> One thing i should stress now, before things get going, code is
> written and patches start flying around, is that in order to get the
> finished code into the eCos repository you need to ensure that all
> contributors have copyright assignments with the FSF. 
>   

As I just read, the copyright assignment cannot be done with the FSF 
yet, and instead is handled by eCosCentric? Is this situation still valid?

> Getting such copyright assignments can be a long slow process. So
> don't let it stop development. However you need to keep track of who
> contributed what so at the end of the development work, you can show
> who has developed it and that they all have copyright assignments.
>   

So how do we get such copyright assignments? Is it sufficient to keep 
track of the developer names in the source files? Additionally a svn log 
could show who contributed to what file. Or what is needed besides?

Simon

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Re: [ECOS] Re: Cortex M3 architecture

[Andrew Lunn]

> As I just read, the copyright assignment cannot be done with the FSF  
> yet, and instead is handled by eCosCentric? Is this situation still 
> valid?

Nope. The Copyright assignment is made with the FSF. See
http://ecos.sourceware.org/assign.html, film the form in and send it
to assign@gnu.org.

> So how do we get such copyright assignments? 

See above.

> Is it sufficient to keep track of the developer names in the source
> files?

Not sufficient, but part of the process. You should use the standard
eCos header files and put the author/contributor into the standard
headers. Also use the standard ChangeLog file, listing each change,
what files where changed and by who.

> Additionally a svn log could show who contributed to what file.

Having a full svn/cvs/git/foobar history for the development, with
individual usernames, is really good. Do that if you can. Also it will
help with the development, so i would encourage it anyway.

           Andrew

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Re: [ECOS] Re: Cortex M3 architecture

[Robin Randhawa]

Hi again and apologies for the delay.

On Wed, 2008-09-03 at 10:07 +0200, simon.kallweit@intefo.ch wrote:

> It's not yet decided, but it seems that my company will use eCos in 
> upcoming projects. As these designs are based on STM32 processors, we 
> would like to invest in the eCos architecture port. So as it seems, I'll 
> get payed time to do the port, and yes, I'm really looking forward to 
> collaborate with others. If my company makes the decision in favor of 
> eCos, I'll start working right away.

Sounds good.

> How much time can you spend, working on the port?

My primary job permitting, a couple of hours on weeknights and more on
weekends, I suppose.

I've been skimming over M3 references. Interesting.

Cheers,
Robin


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