From mboxrd@z Thu Jan  1 00:00:00 1970
From: Peter Graf <p.graf@itknet.de>
To: ecos-discuss@sources.redhat.com
Subject: [ECOS] SH7709A frequency control register
Date: Fri, 20 Apr 2001 07:13:00 -0000
Message-id: <3.0.5.32.20010420161734.00908b60@128.128.128.220>
X-SW-Source: 2001-04/msg00267.html

Hi,

found a bug in the calculation of the value for the SH3 (SH7709A) FRQCR
register in
packages\hal\sh\sh3\current\include\mod_regs_cpg.h

#elif (CYGARC_SH_MOD_CPG == 3) // ---------------------------- V3
...
#elif (CYGHWR_HAL_SH_OOC_DIVIDER_2 == 6)
# define CYGARC_REG_FRQCR_INIT_DIVIDER2 0x2002

Should be 0x2001, at least for my configuration, which is
  SH clock crystal: 11000000
  SH clock PLL circuit 1: 3
  SH clock PLL circuit 2: 4
  SH clock divider 1: 1
  SH clock divider 2: 6
  SH clock mode: 1

Otherwise I get a crash, as soon as the code from platform.inc (derived
from the Hitachi SH7708 board) is executed.

BTW, setting the FRQCR out of the table just like all the other registers
(BCR2, BCR1, ...) might not be a very good idea. Hitachi demands special
treatment after changing this register. (eg. 20 uncached NOPs immediately
after the register write, or access to a peripheral module.)

Peter