public inbox for ecos-discuss@sourceware.org
 help / color / mirror / Atom feed
* [ECOS] Interrupts In MIPS....?
@ 2000-10-03  9:09 Colin Ford
  2000-10-06  5:15 ` Nick Garnett
  0 siblings, 1 reply; 2+ messages in thread
From: Colin Ford @ 2000-10-03  9:09 UTC (permalink / raw)
  To: Ecos Mailing List

Hello,

I've got a bit of a design question. Eventually I want
to service all types of interrupts i.e. Ethernet, DMA,
MII, UART, PCI etc.

The problem I have is that all of these interrupts latch
up to a bit in the "cause" register. Now the question
I have is should I change the "hal_interrupt_handler" to
call another handler to then check which actual
peripheral caused the interrupt which in turn calls the
devices ISR or should I go about it in a different way.

I don't really know the philosophy of eCos enough to
know what would be the best course of action?

Any advice?
Cheers,
Col.

--
===========================================
Colin Ford               PipingHot Networks
Software Engineer        +44 (0)1364 655510



^ permalink raw reply	[flat|nested] 2+ messages in thread

* Re: [ECOS] Interrupts In MIPS....?
  2000-10-03  9:09 [ECOS] Interrupts In MIPS....? Colin Ford
@ 2000-10-06  5:15 ` Nick Garnett
  0 siblings, 0 replies; 2+ messages in thread
From: Nick Garnett @ 2000-10-06  5:15 UTC (permalink / raw)
  To: ecos-discuss

Colin Ford <colin.ford@pipinghotnetworks.com> writes:

> Hello,
> 
> I've got a bit of a design question. Eventually I want
> to service all types of interrupts i.e. Ethernet, DMA,
> MII, UART, PCI etc.
> 
> The problem I have is that all of these interrupts latch
> up to a bit in the "cause" register. Now the question
> I have is should I change the "hal_interrupt_handler" to
> call another handler to then check which actual
> peripheral caused the interrupt which in turn calls the
> devices ISR or should I go about it in a different way.
> 
> I don't really know the philosophy of eCos enough to
> know what would be the best course of action?
> 

Take a look in the VR4373 HAL for the model of what you should do.
The default interrupt VSR chooses a first ISR based on the cause
register bits. Three of the bits are connected to the interrupt
controller and the ISRs for these are springboard ISRs that decode the
controller's registers and revector to a second ISR further down the
table. This is hal_isr_springboard in platform.S in the VRC4373 HAL
package.


-- 
Nick Garnett, eCos Kernel Architect
Red Hat, Cambridge, UK

^ permalink raw reply	[flat|nested] 2+ messages in thread

end of thread, other threads:[~2000-10-06  5:15 UTC | newest]

Thread overview: 2+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2000-10-03  9:09 [ECOS] Interrupts In MIPS....? Colin Ford
2000-10-06  5:15 ` Nick Garnett

This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).