[ECOS] FIQ on ARM

[ECOS] FIQ on ARM

[David Airlie]

Hi all,

I see eCos supports the FIQ on ARM as just another IRQ line, is there any
way to make it use the FIQ as a prioritised interrupt line? I have an IRQ
interrupt that holds the system for a long time and I'd like to allow a
serial FIQ to interrupt it ... but all eCos does is return if the IRQ is
active an allow eCos to service it ..

my current thinking is to remove the return .. but I'm wondering how
re-entrant eCos is at this level, will it handle the situation well..

I know I should re-design my app to do the IRQ in an ISR/DSR and then use
a soft FIFO between ISR/DSR parts of my serial .. but I'm all in for the
quickest path at the moment ....

Dave.

-- 
      David Airlie, Software Engineer, Parthus Technologies plc.,
       Mary Rosse Centre, National Tech Park, Limerick, Ireland.
   t: +353-61-508116 / f: +353-61-508101 / David.Airlie@parthus.com

Re: [ECOS] FIQ on ARM

[Jonathan Larmour]

David Airlie wrote:
> 
> Hi all,
> 
> I see eCos supports the FIQ on ARM as just another IRQ line, is there any
> way to make it use the FIQ as a prioritised interrupt line? I have an IRQ
> interrupt that holds the system for a long time and I'd like to allow a
> serial FIQ to interrupt it ... but all eCos does is return if the IRQ is
> active an allow eCos to service it ..
> 
> my current thinking is to remove the return .. but I'm wondering how
> re-entrant eCos is at this level, will it handle the situation well..

For a start, if you do that you'll stomp on __exception_stack. You'll need
to make a separate __FIQ_exception_stack. After that it may not be too bad
because it shouldn't be terribly different from a nested interrupt. But
there could well be fiddly bits with the mode registers.

Jifl
-- 
Red Hat, Rustat House, Clifton Road, Cambridge, UK. Tel: +44 (1223) 271062
Maybe this world is another planet's Hell -Aldous Huxley || Opinions==mine

Re: [ECOS] FIQ on ARM

[Gary Thomas]

On 14-May-2001 Jonathan Larmour wrote:
> David Airlie wrote:
>> 
>> Hi all,
>> 
>> I see eCos supports the FIQ on ARM as just another IRQ line, is there any
>> way to make it use the FIQ as a prioritised interrupt line? I have an IRQ
>> interrupt that holds the system for a long time and I'd like to allow a
>> serial FIQ to interrupt it ... but all eCos does is return if the IRQ is
>> active an allow eCos to service it ..
>> 
>> my current thinking is to remove the return .. but I'm wondering how
>> re-entrant eCos is at this level, will it handle the situation well..
> 
> For a start, if you do that you'll stomp on __exception_stack. You'll need
> to make a separate __FIQ_exception_stack. After that it may not be too bad
> because it shouldn't be terribly different from a nested interrupt. But
> there could well be fiddly bits with the mode registers.

Actually, this should already work fine.  Are you working from anonCVS?  We
made some significant changes in this area at the end of January, 2001.

I am curious what was meant by the statement "but all eCos does is return if 
the IRQ is active an allow eCos  to service it".  Can you [David] articulate?  
maybe point at the code?

Re: [ECOS] FIQ on ARM

[Jonathan Larmour]

Gary Thomas wrote:
> 
> On 14-May-2001 Jonathan Larmour wrote:
> > David Airlie wrote:
> >>
> >> Hi all,
> >>
> >> I see eCos supports the FIQ on ARM as just another IRQ line, is there any
> >> way to make it use the FIQ as a prioritised interrupt line? I have an IRQ
> >> interrupt that holds the system for a long time and I'd like to allow a
> >> serial FIQ to interrupt it ... but all eCos does is return if the IRQ is
> >> active an allow eCos to service it ..
> >>
> >> my current thinking is to remove the return .. but I'm wondering how
> >> re-entrant eCos is at this level, will it handle the situation well..
> >
> > For a start, if you do that you'll stomp on __exception_stack. You'll need
> > to make a separate __FIQ_exception_stack. After that it may not be too bad
> > because it shouldn't be terribly different from a nested interrupt. But
> > there could well be fiddly bits with the mode registers.
> 
> Actually, this should already work fine.  Are you working from anonCVS?  We
> made some significant changes in this area at the end of January, 2001.
> 
> I am curious what was meant by the statement "but all eCos does is return if
> the IRQ is active an allow eCos  to service it".  Can you [David] articulate?
> maybe point at the code?

David means this bit:

        // If FIQ interrupted IRQ mode, just return with FIQ disabled.
        // The common interrupt handling takes care of the rest.
        orr     r8,r8,#CPSR_FIQ_DISABLE
        msr     spsr,r8
        subs    pc,lr,#4

I believe this means that the FIQ gets processed after the current IRQ. And
if we already have an IRQ, the FIQ could be interrupting it at any point,
such as when it's using __exception_stack.

Jifl
-- 
Red Hat, Rustat House, Clifton Road, Cambridge, UK. Tel: +44 (1223) 271062
Maybe this world is another planet's Hell -Aldous Huxley || Opinions==mine

Re: [ECOS] FIQ on ARM

[Mark Salter]

>>>>> Jonathan Larmour writes:

>         // If FIQ interrupted IRQ mode, just return with FIQ disabled.
>         // The common interrupt handling takes care of the rest.
>         orr     r8,r8,#CPSR_FIQ_DISABLE
>         msr     spsr,r8
>         subs    pc,lr,#4

> I believe this means that the FIQ gets processed after the current IRQ. And
> if we already have an IRQ, the FIQ could be interrupting it at any point,
> such as when it's using __exception_stack.

That's not exactly the case. There is only a small window where FIQ can
interrupt IRQ mode. Notice, the IRQ handler switches to supervior mode
early on. So, if there is an IRQ and FIQ interrupts it before the switch
to SVR mode, the FIQ handler returns to the IRQ handler with FIQ disabled.
The common interrupt handling will eventually call hal_IRQ_handler in the
platform HAL. It is there that you could give priority to FIQs over IRQs.

--Mark

Re: [ECOS] FIQ on ARM

[Rafael Rodríguez Velilla]

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What about using?

cyg_interrupt_set_vsr ((cyg_vector_t) 7, cyg_VSR_t *vsr);

  Where the pointer to vsr is the address where starts an assembly routine
that you have to program to service your FIQ.  Remember that you have to
manage your own stack and that you have to implement a safe way to return to
eCos.

  If you use this you can program a very quick response for your FIQ. This
still has the problem with the IRQ, which is non-reentrant (eCos 1.3.1, I
don't know if this is still true with CVS versions), if you want to mend
this you'll need to mess with the source code of eCos.
  Instead of this, surely you'd prefer partitioning your interrupt service
into a short ISR and its corresponding DSR, this seems to me the quickest
path.



> I see eCos supports the FIQ on ARM as just another IRQ line, is there any
> way to make it use the FIQ as a prioritised interrupt line? I have an IRQ
> interrupt that holds the system for a long time and I'd like to allow a
> serial FIQ to interrupt it ... but all eCos does is return if the IRQ is
> active an allow eCos to service it ..
>
> my current thinking is to remove the return .. but I'm wondering how
> re-entrant eCos is at this level, will it handle the situation well..
>
> I know I should re-design my app to do the IRQ in an ISR/DSR and then use
> a soft FIFO between ISR/DSR parts of my serial .. but I'm all in for the
> quickest path at the moment ....
>
> Dave.
>
> --
>       David Airlie, Software Engineer, Parthus Technologies plc.,
>        Mary Rosse Centre, National Tech Park, Limerick, Ireland.
>    t: +353-61-508116 / f: +353-61-508101 / David.Airlie@parthus.com

--
Rafael Rodríguez Velilla        rrv@tid.es
Telefónica I+D          http://www.tid.es
Telf: +34 - 91 337 4270

Re: [ECOS] FIQ on ARM

[David Airlie]

Hi all,
	I'm working on a stack from the 26th Feb, 2001, (it's been ported
to an internal board), I've noticed that my HAL routines such as
hal_IRQ_handler and friends don't investigate FIQ registers which I would
have to add, in another project we've used our own code on a separate FIQ
fine, but for this I need to get the eCos serial code to run from the
FIQ...

I'm hearing now from my group that I might be able to get away with
DSR'ing the long running interrupt and then using a soft FIFO between ISR
and DSR for the serial (v. small FIFO)... my long running interrupt is
fairly long... and run everyone from IRQ land ..

Thanks for your help,

Dave.

> 
> Actually, this should already work fine.  Are you working from anonCVS?  We
> made some significant changes in this area at the end of January, 2001.
> 
> I am curious what was meant by the statement "but all eCos does is return if 
> the IRQ is active an allow eCos  to service it".  Can you [David] articulate?  
> maybe point at the code?
> 

-- 
      David Airlie, Software Engineer, Parthus Technologies plc.,
       Mary Rosse Centre, National Tech Park, Limerick, Ireland.
   t: +353-61-508116 / f: +353-61-508101 / David.Airlie@parthus.com

Re: [ECOS] FIQ on ARM

[rob.wj.jansen]

Dave,

> I know I should re-design my app to do the IRQ in an ISR/DSR and then use
> a soft FIFO between ISR/DSR parts of my serial .. but I'm all in for the
> quickest path at the moment ....

the quickest path will be to split this into ISR/DSR. Otherwise you'll have
to change the startup to split the shared FIQ/IRQ routines.
This "soft FIFO" you're talking about looks like overkill, specially since
you do not allow IRQs in IRQs.
Depending on what kind of device the interrupt comes from, you might use
the ISR to just schedule the DSR.

I used an ISR function with just a "return CYG_ISR_CALL_DSR" to schedule the
routine that reads the (hardware) FIFO from the device.

Regards,

	Rob Jansen