[ECOS] Cache problem in the AEB board (lh77790b) (Jesper?)

[ECOS] Cache problem in the AEB board (lh77790b) (Jesper?)

[Guillermo Rodriguez Garcia]

Hi all,

I am unsuccessfully trying to enable the cache in the AEB board
(lh77790b chip). I know that the cache was broken in the first
revisions which included the lh77790a, but according to Sharp it
should be working on the lh77790b (AEB rev C).

I found this in the sources:

// AEB rev C has 256kB of memory. Cache is working (set cachable)
#if 0
#define AEB_SRAM .long	0xFFFFA008,0x00008000,0x00048000,0x00007c04
#define AEB_BAD  .long	0xFFFFA00C,0x00048000,0x01000000,0x00000000
#else
// FIXME: There is a cache problem of some sort. Either eCos or the
// chip. Leave cache disabled till I find the time to fix it. Jesper
#define AEB_SRAM .long	0xFFFFA008,0x00008000,0x00048000,0x00007804
#define AEB_BAD  .long	0xFFFFA00C,0x00048000,0x01000000,0x00000000
#endif

Could someone (Jesper?) give some details about what work has
already been done on this issue?

Thanks,
G.

Re: [ECOS] Cache problem in the AEB board (lh77790b) (Jesper?)

[Jonathan Larmour]

Guillermo Rodriguez Garcia wrote:
> 
> Hi all,
> 
> I am unsuccessfully trying to enable the cache in the AEB board
> (lh77790b chip). I know that the cache was broken in the first
> revisions which included the lh77790a, but according to Sharp it
> should be working on the lh77790b (AEB rev C).
> 
> I found this in the sources:
> 
> // AEB rev C has 256kB of memory. Cache is working (set cachable)
> #if 0
> #define AEB_SRAM .long  0xFFFFA008,0x00008000,0x00048000,0x00007c04
> #define AEB_BAD  .long  0xFFFFA00C,0x00048000,0x01000000,0x00000000
> #else
> // FIXME: There is a cache problem of some sort. Either eCos or the
> // chip. Leave cache disabled till I find the time to fix it. Jesper
> #define AEB_SRAM .long  0xFFFFA008,0x00008000,0x00048000,0x00007804
> #define AEB_BAD  .long  0xFFFFA00C,0x00048000,0x01000000,0x00000000
> #endif
> 
> Could someone (Jesper?) give some details about what work has
> already been done on this issue?

You're already looking at it alas. The best thing to do now is to try
enabling it and see how it dies and try to fix it. Here's what Jesper wrote
about it at one point:

 Trying to fix AEB/c problems - ran three loops with cache enabled -
 is indeed faster (3x). Then dies. Register rot during interrupt -
 suspect multi-store/load instructions.

Jifl
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