From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 31471 invoked by alias); 18 May 2005 05:42:43 -0000 Mailing-List: contact ecos-discuss-help@ecos.sourceware.org; run by ezmlm Precedence: bulk List-Subscribe: List-Archive: List-Post: List-Help: , Sender: ecos-discuss-owner@ecos.sourceware.org Received: (qmail 30885 invoked from network); 18 May 2005 05:42:37 -0000 Received: from unknown (HELO mout.alturo.net) (212.227.15.21) by sourceware.org with SMTP; 18 May 2005 05:42:37 -0000 Received: from [212.227.15.31] (helo=mrelay.alturo.net) by mout.alturo.net with esmtp (Exim 3.35 #1) id 1DYHKG-0007Xj-00; Wed, 18 May 2005 07:42:36 +0200 Received: from [84.56.145.92] (helo=[192.168.2.103]) by mrelay.alturo.net with asmtp (Exim 3.35 #1) id 1DYHKG-0001Jg-00; Wed, 18 May 2005 07:42:36 +0200 Message-ID: <428AD5CA.4080900@ovidius-ib.de> Date: Wed, 18 May 2005 09:49:00 -0000 From: Marcel Ovidiu Achim User-Agent: Mozilla Thunderbird 0.8 (Windows/20040913) MIME-Version: 1.0 To: marcel.achim@ovidius-ib.de CC: ecos-discuss@sources.redhat.com, ecos-discuss@ecos.sourceware.org References: In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Subject: [ECOS] AT91 on EB55 DSR is started only once X-SW-Source: 2005-05/txt/msg00231.txt.bz2 Dear all, I am experiencing some weird behaviour when trying to setup a timer interrupt on an EB55 board. I attached the relevant code below. What happens is that the DSR is started only once after init from main, and then never again, although the timer interrupt is shown to occur (on an ascilloscope). By accident I discovered that this can be fixed if I insert the following line in the DSR: HAL_READ_UINT32( AT91_TC1 + AT91_TC_SR, i ); Although the read seems to have no impact of the content of the SR register, it seems to magically have the DSR activated again. I could live fine with that, but then other external interrupts seem to considerably bring down overall system performance. What am I overseeing here? Can anyone please help? Thanks, void main() { ... // Create interrupt for Timer3 with prio 10 cyg_interrupt_create( CYGNUM_HAL_INTERRUPT_TIMER3, 10, 0, Timer_ISR, Timer_DSR, &handle_timer_isr, &isr ); cyg_interrupt_attach(handle_timer_isr); // AIC Source Mode Register. TC3 interupt on a positive edge of the TC3 timer. HAL_WRITE_UINT32( AT91_AIC + AT91_AIC_SMR9, AT91_AIC_SMR_EDGE_POS); // AIC Source Mode Register. IRQ0 positive edge-triggerd HAL_WRITE_UINT32( AT91_AIC + AT91_AIC_SMR29, AT91_AIC_SMR_EDGE_POS); // AIC Source Mode Register. IRQ1 positive edge-triggerd HAL_WRITE_UINT32( AT91_AIC + AT91_AIC_SMR28, 0x00000060); // // CLOCK CONFIGURATION // // Generate interrupt on RC compare HAL_WRITE_UINT32( 0x00 + AT91_TC1 + AT91_TC_IER, AT91_TC_IER_CPC); // Fill RC register with a value HAL_WRITE_UINT32( 0x00 + AT91_TC1 + AT91_TC_RC, 0x00003FFF); // TC command register. Set the frequency for the timer, enabel Wave Mode and // on RC compare reset the timer and start it again. HAL_WRITE_UINT32( 0x00 + AT91_TC1 + AT91_TC_CMR, AT91_TC_CMR_CLKS_MCK2 | AT91_TC_CMR_WAVE | AT91_TC_CMR_CPCTRG | AT91_TC_CMR_ACPC_TOGGLE ); // Enable and start the timer HAL_WRITE_UINT32( 0x00 + AT91_TC1 + AT91_TC_CCR, 0x01 + 0x04); ... // Enable interrupts cyg_interrupt_enable(); } cyg_uint32 Timer_ISR(cyg_vector_t vector, cyg_addrword_t data) { // Block this interrupt from occurring until DSR completed cyg_interrupt_mask (vector); // Ack the interrupt so other routines can be serviced cyg_interrupt_acknowledge(vector); // Proceed to DSR return CYG_ISR_CALL_DSR; } void Timer_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data) { int i=0; if ( some_global_condition ) { execute_code(); } HAL_READ_UINT32( AT91_TC1 + AT91_TC_SR, i ); // Allow this interrupt to occur again cyg_interrupt_unmask (vector); } -- Before posting, please read the FAQ: http://ecos.sourceware.org/fom/ecos and search the list archive: http://ecos.sourceware.org/ml/ecos-discuss From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 31736 invoked by alias); 18 May 2005 05:42:45 -0000 Mailing-List: contact ecos-discuss-help@ecos.sourceware.org; run by ezmlm Precedence: bulk List-Subscribe: List-Archive: List-Post: List-Help: , Sender: ecos-discuss-owner@ecos.sourceware.org Received: (qmail 30885 invoked from network); 18 May 2005 05:42:37 -0000 Received: from unknown (HELO mout.alturo.net) (212.227.15.21) by sourceware.org with SMTP; 18 May 2005 05:42:37 -0000 Received: from [212.227.15.31] (helo=mrelay.alturo.net) by mout.alturo.net with esmtp (Exim 3.35 #1) id 1DYHKG-0007Xj-00; Wed, 18 May 2005 07:42:36 +0200 Received: from [84.56.145.92] (helo=[192.168.2.103]) by mrelay.alturo.net with asmtp (Exim 3.35 #1) id 1DYHKG-0001Jg-00; Wed, 18 May 2005 07:42:36 +0200 Message-ID: <428AD5CA.4080900@ovidius-ib.de> Date: Wed, 18 May 2005 10:11:00 -0000 From: Marcel Ovidiu Achim User-Agent: Mozilla Thunderbird 0.8 (Windows/20040913) MIME-Version: 1.0 To: marcel.achim@ovidius-ib.de CC: ecos-discuss@sources.redhat.com, ecos-discuss@ecos.sourceware.org References: In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Subject: [ECOS] AT91 on EB55 DSR is started only once X-SW-Source: 2005-05/txt/msg00232.txt.bz2 Message-ID: <20050518101100.bOa76wPzcTAWJEo-v1QG9yVOCTaRHfptgc-Bq0s0UvI@z> Dear all, I am experiencing some weird behaviour when trying to setup a timer interrupt on an EB55 board. I attached the relevant code below. What happens is that the DSR is started only once after init from main, and then never again, although the timer interrupt is shown to occur (on an ascilloscope). By accident I discovered that this can be fixed if I insert the following line in the DSR: HAL_READ_UINT32( AT91_TC1 + AT91_TC_SR, i ); Although the read seems to have no impact of the content of the SR register, it seems to magically have the DSR activated again. I could live fine with that, but then other external interrupts seem to considerably bring down overall system performance. What am I overseeing here? Can anyone please help? Thanks, void main() { ... // Create interrupt for Timer3 with prio 10 cyg_interrupt_create( CYGNUM_HAL_INTERRUPT_TIMER3, 10, 0, Timer_ISR, Timer_DSR, &handle_timer_isr, &isr ); cyg_interrupt_attach(handle_timer_isr); // AIC Source Mode Register. TC3 interupt on a positive edge of the TC3 timer. HAL_WRITE_UINT32( AT91_AIC + AT91_AIC_SMR9, AT91_AIC_SMR_EDGE_POS); // AIC Source Mode Register. IRQ0 positive edge-triggerd HAL_WRITE_UINT32( AT91_AIC + AT91_AIC_SMR29, AT91_AIC_SMR_EDGE_POS); // AIC Source Mode Register. IRQ1 positive edge-triggerd HAL_WRITE_UINT32( AT91_AIC + AT91_AIC_SMR28, 0x00000060); // // CLOCK CONFIGURATION // // Generate interrupt on RC compare HAL_WRITE_UINT32( 0x00 + AT91_TC1 + AT91_TC_IER, AT91_TC_IER_CPC); // Fill RC register with a value HAL_WRITE_UINT32( 0x00 + AT91_TC1 + AT91_TC_RC, 0x00003FFF); // TC command register. Set the frequency for the timer, enabel Wave Mode and // on RC compare reset the timer and start it again. HAL_WRITE_UINT32( 0x00 + AT91_TC1 + AT91_TC_CMR, AT91_TC_CMR_CLKS_MCK2 | AT91_TC_CMR_WAVE | AT91_TC_CMR_CPCTRG | AT91_TC_CMR_ACPC_TOGGLE ); // Enable and start the timer HAL_WRITE_UINT32( 0x00 + AT91_TC1 + AT91_TC_CCR, 0x01 + 0x04); ... // Enable interrupts cyg_interrupt_enable(); } cyg_uint32 Timer_ISR(cyg_vector_t vector, cyg_addrword_t data) { // Block this interrupt from occurring until DSR completed cyg_interrupt_mask (vector); // Ack the interrupt so other routines can be serviced cyg_interrupt_acknowledge(vector); // Proceed to DSR return CYG_ISR_CALL_DSR; } void Timer_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data) { int i=0; if ( some_global_condition ) { execute_code(); } HAL_READ_UINT32( AT91_TC1 + AT91_TC_SR, i ); // Allow this interrupt to occur again cyg_interrupt_unmask (vector); } -- Before posting, please read the FAQ: http://ecos.sourceware.org/fom/ecos and search the list archive: http://ecos.sourceware.org/ml/ecos-discuss