Re: [ECOS] ROMRAM startup mode om powerpc

[Gary Thomas <gary@mlbassoc.com>]

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Georg Brutscheid wrote:
> Hi all,
> 
> 
> I am trying to use the ROMRAM startup mode on a powerpc board. As a reference I took the Viper board. 
> The differcene to that board is the address mapping. 4MB FLASH at address 0 and 4 MB SRAM at address 0x400000. 
> 
> I copied the mlt_powerpc_xxx_romram.ldi and *.h from Viper board, but that seems to be for RAM mode and 
> nothing has to be copied from flash to ram. 
> 
> mlt_powerpc_xxx_romram.ldi
> 
> #include <cyg/infra/cyg_type.inc>
> 
> MEMORY
> {
>     ram : ORIGIN = 0x0400000, LENGTH = 0x400000
> }
> 
> SECTIONS
> {
>     SECTIONS_BEGIN
>     SECTION_vectors (ram, 0x0400000, LMA_EQ_VMA)
>     SECTION_text (ram, 0x403400, LMA_EQ_VMA)
>     SECTION_fini (ram, ALIGN (0x4), LMA_EQ_VMA)
>     SECTION_rodata1 (ram, ALIGN (0x8), LMA_EQ_VMA)
>     SECTION_rodata (ram, ALIGN (0x8), LMA_EQ_VMA)
>     SECTION_fixup (ram, ALIGN (0x4), LMA_EQ_VMA)
>     SECTION_gcc_except_table (ram, ALIGN (0x1), LMA_EQ_VMA)
>     SECTION_data (ram, ALIGN (0x8), LMA_EQ_VMA)
>     SECTION_sbss (ram, ALIGN (0x4), LMA_EQ_VMA)
>     SECTION_bss (ram, ALIGN (0x10), LMA_EQ_VMA)
>     CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
>     SECTIONS_END
> }
> 
> mlt_powerpc_xxx_romram.h
> 
> // eCos memory layout - Thu May 30 10:05:45 2002
> 
> // This is a generated file - do not edit
> 
> #ifndef __ASSEMBLER__
> #include <cyg/infra/cyg_type.h>
> #include <stddef.h>
> 
> #endif
> #define CYGMEM_REGION_ram (0x400000)
> #define CYGMEM_REGION_ram_SIZE (0x400000)
> #define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
> #ifndef __ASSEMBLER__
> extern char CYG_LABEL_NAME (__heap1) [];
> #endif
> #define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
> #define CYGMEM_SECTION_heap1_SIZE (0x400000 - (size_t) CYG_LABEL_NAME (__heap1))
> 
> 
> 
> Then I changed the mlt_powerpc_xxx_romram.ldi and *h files, I used settings which I found for the VADS board. 
> 
> 
> 
> #include <cyg/infra/cyg_type.inc>
> 
> MEMORY
> {
>     ram : ORIGIN = 0x0400000, LENGTH = 0x400000
>     rom : ORIGIN = 0x0000000, LENGTH = 0x400000
> }
> 
> SECTIONS
> {
>     SECTIONS_BEGIN
>     SECTION_vectors (rom, 0, LMA_EQ_VMA)
>     SECTION_text (rom, ALIGN (0x4), LMA_EQ_VMA)
>     SECTION_fini (rom, ALIGN (0x4), LMA_EQ_VMA)
>     SECTION_rodata1 (rom, ALIGN (0x8), LMA_EQ_VMA)
>     SECTION_rodata (rom, ALIGN (0x8), LMA_EQ_VMA)
>     SECTION_fixup (rom, ALIGN (0x4), LMA_EQ_VMA)
>     SECTION_gcc_except_table (rom, ALIGN (0x1), LMA_EQ_VMA)
>   CYG_LABEL_DEFN(__reserved_vectors) = 0; . =      CYG_LABEL_DEFN(__reserved_vectors) + 0x3000;
>     CYG_LABEL_DEFN(__reserved_vsr_table) = ALIGN (0x1); . = CYG_LABEL_DEFN(__reserved_vsr_table) + 0x200;
>     CYG_LABEL_DEFN(__reserved_virtual_table) = ALIGN (0x1); . = CYG_LABEL_DEFN(__reserved_virtual_table) + 0x100;
>     CYG_LABEL_DEFN(__reserved_for_flash)     = ALIGN (0x1); . = CYG_LABEL_DEFN(__reserved_for_flash)     + 0xcd00;
>     SECTION_data (ram, ALIGN (0x10), FOLLOWING (.gcc_except_table))
>     SECTION_sbss (ram, ALIGN (0x4), LMA_EQ_VMA)
>     SECTION_bss (ram, ALIGN (0x10), LMA_EQ_VMA)
>     CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
>     SECTIONS_END
> }
> 
>  
> In this case the linker conplained that the "section .data is not within region ram", which is correct. 
> What is the right setting for data section in my case? I think I can not use a fix ram address here since the ram_data_end is used in the copy routine.
> 
> 
> The coping from flash to ram is done here:
> 
> #ifdef CYG_HAL_STARTUP_ROMRAM
>         // Copy image from ROM to RAM
>         mflr    r3              
>         lwi     r4,0x0
>         lwi     r5,0x01FFFFF    // ROM/FLASH base
>         and     r3,r3,r5             // segment relative
>         lwi     r6,_hal_hardware_init_done
>         mtlr    r6
>         sub     r6,r3,r6        // Absolute address
>         add     r6,r6,r4        // FLASH address
>         lwi     r7,0x400000     // where to copy to
>         lwi     r8,__ram_data_end
> 10:     lwz     r5,0(r6)
>         stw     r5,0(r7)
>         addi    r6,r6,4
>         addi    r7,r7,4
>         cmplw   r7,r8
>         bne     10b
> #endif                
> 
> When (in which file) does the jump from flash to ram takes place?

For the linker, ROMRAM mode looks pretty much like RAM mode
in that all addresses are in RAM.  The startup code (e.g. viper.S)
expects to run in ROM and it copies the code into RAM.  It
jumps into RAM by adjusting the return address (this is done
fairly early in the hal_hardware_init function and is the same
for ROM and ROMRAM mode).

Note: you may have some adjusting to do as PowerPC boards normally
have RAM at 0 and ROM somewhere else.  Why don't you set it up this
way - depending on the processor, you have full control over this.

What PowerPC processor are you using?  The 8xx and 82xx chips have
BRx/ORx registers that establish the physical address mapping for
various segments (chip selects), which makes it easy to have RAM
at 0 and ROM elsewhere.

- --
- ------------------------------------------------------------
Gary Thomas                 |  Consulting for the
MLB Associates              |    Embedded world
- ------------------------------------------------------------
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