* [ECOS] Init sequence for enabling MMU at mpc5xx fails
@ 2008-07-22 15:29 Andrey Baboshin
2008-07-22 15:34 ` Andrey Baboshin
2008-07-22 15:46 ` Gary Thomas
0 siblings, 2 replies; 3+ messages in thread
From: Andrey Baboshin @ 2008-07-22 15:29 UTC (permalink / raw)
To: ecos-discuss
Hi, all.
I find following problem.
I enable the MMU in eCos and it executes next code
# Initialize MMU.
bl hal_MMU_init
# Enable MMU (if desired) so we can safely enable caches.
lwi r3,CYG_MSR # interrupts enabled later
sync
mtmsr r3 (*)
sync
# Enable caches
bl hal_enable_caches
I have found it fails after (*).
In additional
CYG_MSR = (CYG_MSR_COMMON | IP_BIT | IR_DR_BITS)
CYG_MSR_COMMON = (MSR_FP | MSR_ME | MSR_RI)
IP_BIT = 0
IR_DR_BITS = (MSR_IR | MSR_DR)
Do have anyone some problem?
It works only when I comment mtmsr r3 and followed by it sync.
---
Andrey Baboshin
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^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [ECOS] Init sequence for enabling MMU at mpc5xx fails
2008-07-22 15:29 [ECOS] Init sequence for enabling MMU at mpc5xx fails Andrey Baboshin
@ 2008-07-22 15:34 ` Andrey Baboshin
2008-07-22 15:46 ` Gary Thomas
1 sibling, 0 replies; 3+ messages in thread
From: Andrey Baboshin @ 2008-07-22 15:34 UTC (permalink / raw)
To: ecos-discuss
oops.
I'm sorry - MPC8xx series (MPC852T).
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^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [ECOS] Init sequence for enabling MMU at mpc5xx fails
2008-07-22 15:29 [ECOS] Init sequence for enabling MMU at mpc5xx fails Andrey Baboshin
2008-07-22 15:34 ` Andrey Baboshin
@ 2008-07-22 15:46 ` Gary Thomas
1 sibling, 0 replies; 3+ messages in thread
From: Gary Thomas @ 2008-07-22 15:46 UTC (permalink / raw)
To: Andrey Baboshin; +Cc: ecos-discuss
Andrey Baboshin wrote:
> Hi, all.
>
> I find following problem.
> I enable the MMU in eCos and it executes next code
>
> # Initialize MMU.
> bl hal_MMU_init
>
> # Enable MMU (if desired) so we can safely enable caches.
> lwi r3,CYG_MSR # interrupts enabled later
> sync
> mtmsr r3 (*)
> sync
>
> # Enable caches
> bl hal_enable_caches
>
> I have found it fails after (*).
> In additional
> CYG_MSR = (CYG_MSR_COMMON | IP_BIT | IR_DR_BITS)
> CYG_MSR_COMMON = (MSR_FP | MSR_ME | MSR_RI)
> IP_BIT = 0
> IR_DR_BITS = (MSR_IR | MSR_DR)
>
> Do have anyone some problem?
> It works only when I comment mtmsr r3 and followed by it sync.
Which only means that it works with the MMU turned off :-(
How did you setup the MMU?
What target/platform are you working with?
--
------------------------------------------------------------
Gary Thomas | Consulting for the
MLB Associates | Embedded world
------------------------------------------------------------
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2008-07-22 15:29 [ECOS] Init sequence for enabling MMU at mpc5xx fails Andrey Baboshin
2008-07-22 15:34 ` Andrey Baboshin
2008-07-22 15:46 ` Gary Thomas
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