[ECOS] Re: Init sequence for enabling MMU at mpc5xx fails

[ECOS] Re: Init sequence for enabling MMU at mpc5xx fails

[Anthony Tonizzo]

Andrey:

The MMU uses burst access to DRAM. It might very well be that
your burst patterns in the UPM memory are not quite correct.
You can check this by setting the BIH bit in the ORx register
for your DRAM. This will inhibit the use of UPM burst patterns and
use single beat patterns instead. If your board now works after
you enable the MMU, then you know where where to look.

Tony

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Re: [ECOS] Re: Init sequence for enabling MMU at mpc5xx fails

[Gary Thomas]

Anthony Tonizzo wrote:
> Andrey:
> 
> The MMU uses burst access to DRAM. It might very well be that
> your burst patterns in the UPM memory are not quite correct.
> You can check this by setting the BIH bit in the ORx register
> for your DRAM. This will inhibit the use of UPM burst patterns and
> use single beat patterns instead. If your board now works after
> you enable the MMU, then you know where where to look.

Correct, but bursts only happen when doing cache operations.
On this hardware, the cache is not enabled until later - after
the point where Andrey's code is failing.

More likely is that the MMU setup does not include the ROM/FLASH
or RAM (stack) or even the CPU registers.  All of these must be
mapped (one-to-one, but mapped nonetheless) before the MMU can be
enabled.

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Gary Thomas                 |  Consulting for the
MLB Associates              |    Embedded world
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