[ECOS] ARM7 ADC drivers - any progress?

[ECOS] ARM7 ADC drivers - any progress?

[Steven Clugston]

Hi

I want to use an ARM7 board running eCos for a battery charge monitor / UPS type application for which I need ADC support.

I need a small and cheap standalone board for this and I have identified Olimex SAM7-MT-256 (AT91SAM7S256) and Olimex LPC-MT-2138 as possible candidates.
Reading back through the archives there has been recent discussion about an AT91 ADC driver and an LPC2xxx ADC driver modified from the LPC24xx driver:

AT91:
http://sourceware.org/ml/ecos-discuss/2008-10/msg00018.html

LPC2xxx:
http://sourceware.org/ml/ecos-discuss/2008-12/msg00176.html

Has there been any more progress with these?

Are they likely to be contributed or made available anytime soon?

Thanks,

Steven

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Before posting, please read the FAQ: http://ecos.sourceware.org/fom/ecos
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Re: [ECOS] ARM7 ADC drivers - any progress?

[Robert Brusa]

[-- Attachment #1: Type: text/plain, Size: 1332 bytes --]

On Mon, 18 May 2009 15:50:32 +0200, Steven Clugston  
<steven.clugston@newcastle.ac.uk> wrote:

> Hi
>
> I want to use an ARM7 board running eCos for a battery charge monitor /  
> UPS type application for which I need ADC support.
>
> I need a small and cheap standalone board for this and I have identified  
> Olimex SAM7-MT-256 (AT91SAM7S256) and Olimex LPC-MT-2138 as possible  
> candidates.
> Reading back through the archives there has been recent discussion about  
> an AT91 ADC driver and an LPC2xxx ADC driver modified from the LPC24xx  
> driver:
>
> AT91:
> http://sourceware.org/ml/ecos-discuss/2008-10/msg00018.html
>
> LPC2xxx:
> http://sourceware.org/ml/ecos-discuss/2008-12/msg00176.html
>
> Has there been any more progress with these?
>
> Are they likely to be contributed or made available anytime soon?
>
> Thanks,
>
> Steven
>
> --
> Before posting, please read the FAQ: http://ecos.sourceware.org/fom/ecos
> and search the list archive: http://ecos.sourceware.org/ml/ecos-discuss
>
Hi Steven
I am not familiar with the processors you mention, but I have written a  
module
that uses the adc of the AT91SAM7X. Its not ready to go into ecos (as part  
of ecos), but it integrates smoothly into an ecos-based application - and  
it works. It may (or may not :-( ) be helpfull for you.

Best regards
   Robert


[-- Attachment #2: sun.c --]
[-- Type: application/octet-stream, Size: 12274 bytes --]


/*==============================================================================
System  :       INTRA S/W                                   Copyright 2008..
                ================================================================
                BRUSAG, Sensorik & messtechn.               ph: +41 44 926 74 74
                Entwicklungen,                              fx: +41 44 926 73 34
                Chapfwiesenstr. 14                          em: rbrusa@brusag.ch
                CH-8712 Staefa (Switzerland)                http://www.brusag.ch
================================================================================
SWSystem:	eCOS and toolchain arm-elf-gcc (GCC) 3.2.1 (eCosCentric)
Target:		INTRA Controller with AT91SAM7X-256
Abstract:	Sunsensor and low level handling of ADC of the AT91SAM7X.
	channel assignments are:
	0:	UPWR	VDC	DC power (24 VDCnom) from a voltage divider
	1:	UTEMP	°C	KTY13-6-based temperature sensor of board temperature
	2:	UCUR0	mA	current from base-shunt of motor0-driver
	3:	UCUR1	mA	current from base-shunt of motor1-driver
	4:	q0		V	Signal from sun-sensor quadrant 0
	5:	q1		V	Signal from sun-sensor quadrant 1
	4:	q2		V	Signal from sun-sensor quadrant 2
	7:	q3		V	Signal from sun-sensor quadrant 3

	This ADC-handler uses timer-counter 2 to trigger periodic sampling of all its 8
	channels. Data are stored in ram by dma-transfer. The interrupt routine and the
	associeted DSR implement higher level funktionality.

	Except for ch2 and 3, all all signals are slowly varying. ch2 and 3,
	are filtered with a 10k/100n=1 ms-RC-filter. Let's go for a 1 kHz sampling
	of all channels. We then take mean values sampled during 20 ms (50 Hz lines)
	At places with a 60 Hz line frequncy, the sampling is set for 5/6 ms.
	Irrespective of the lf, a full period consists of 20 readings.. We use TC2
	to produce periodic trigger events for the ADCs DMA.

	The ADC is read in an interrupt driven loop. We calculate means of all 8
	channels and these 8 readings are available by suitable function/routine
	calls.
--------------------------------------------------------------------------------
Edit history:
20-Oct-08 RWB:	Creation
*/
#include <cyg/hal/drv_api.h>
#include <cyg/infra/cyg_type.h>		// basic types for AT91-hardware
#include <cyg/hal/hal_io.h>			// registers and fields of AT91-hardware
#include "ihw.h"
#include "sun.h"
#include "EEProm.h"

#define DMACNT 8					// size of dma-buffer
#define SAMPLES (20 * 5)			// number of adc-samples - a full periode
// of the line frequency corresponds to 20 samples and one should always go
// for an integer multiple of this period.
#define VREF 3.3		// just for now - later from eeprom?
#define ADRES VREF/1023.0	// ad resolution in volts

typedef struct adc_t {
	cyg_uint16 adcbuf[DMACNT];	// data-buffer for dma - actually number of channels
	cyg_uint32 ig,ip;			// get and put pointer for sumadc
	cyg_uint32 sumadc[2][8];	// data for adc-isr - 2 ring-buffers
	cyg_uint32 scancnt[2];		// number of scans in cor buffer
	cyg_uint32 sumsvd[8];		// saved sum of SAMPLES readings
	cyg_uint32 svdcnt;			// counter of summed values
	cyg_uint32 scnt;			// increments with each update of sumsvd/phys
	float volt[8];				// will get volts computed from sumadc
} adc_t;

// module-variables ============================================================
adc_t adcdata;	// buffers for DMA and calculations
static cyg_interrupt adc_int;	// memory for interupt handler
static cyg_handle_t adc_handle;	// handle for interrupt handler
#if SUN_TST & 1
	#include <cyg/io/io.h>
	static cyg_io_handle_t myio1;
	static cyg_uint32 showcnt = 0;
#endif


// internal functions ==========================================================

void SetupADCdata( void )
{
	cyg_uint32 j, ch;
	for (j = 0; j < 2; j++) {
		adcdata.scancnt[j] = 0;	// isr will reset sums if scancnt is 0
	}
	adcdata.svdcnt = 0;
	for (ch = 0; ch < 8; ch++) {
		adcdata.sumsvd[ch] = 0;
		adcdata.volt[ch] = 0.0;
	}
	adcdata.svdcnt = 0; adcdata.scnt = 0;
	adcdata.ip = 0; adcdata.ig = 0;	// buffers empty
} // end SetupADCdata


// interrupt service routines ==================================================

cyg_uint32  adc_isr(cyg_vector_t vector, cyg_addrword_t data)
{
	cyg_uint32 ch, result, sr;
	HAL_READ_UINT32(AT91_ADC + AT91_ADC_SR, sr);	//get status, but required?
	if ( sr != 0xC0000){
	    HAL_WRITE_UINT32(AT91_ADC + AT91_ADC_RPR, (cyg_uint32)&adcdata.adcbuf);
	    HAL_WRITE_UINT32(AT91_ADC + AT91_ADC_RCR, DMACNT);
		cyg_drv_interrupt_acknowledge(vector );
		return CYG_ISR_HANDLED;	// overrun or other bad data
	}

	if (adcdata.scancnt[adcdata.ip]) {
		for (ch = 0; ch < 8; ch++)	// sum up readings stored in adcbuf
			adcdata.sumadc[adcdata.ip][ch] += adcdata.adcbuf[ch];
	}
	else { // reset sums to first value
		for (ch = 0; ch < 8; ch++)	// sum up readings stored in adcbuf
			adcdata.sumadc[adcdata.ip][ch] = adcdata.adcbuf[ch];
	}
	adcdata.scancnt[adcdata.ip]++; // count number of scans
	if (adcdata.scancnt[adcdata.ip] >= SAMPLES) { // need to switch sum-buffers?
		adcdata.ip = (adcdata.ip + 1) & 1;	// Yes, buffer 0 or 1
		if (adcdata.ip == adcdata.ig)	// bufferoverflow?
			adcdata.ig = (adcdata.ig + 1) & 1;	// drop outdated values
			adcdata.scancnt[adcdata.ip] = 0;	// will force a reset of sums
			result = (CYG_ISR_CALL_DSR | CYG_ISR_HANDLED);
	} else result = CYG_ISR_HANDLED;
	// update dma address and counter
    HAL_WRITE_UINT32(AT91_ADC + AT91_ADC_RPR, (cyg_uint32)&adcdata.adcbuf);
    HAL_WRITE_UINT32(AT91_ADC + AT91_ADC_RCR, DMACNT);
	cyg_drv_interrupt_acknowledge(vector );
	return result;
} // end adc_isr

void adc_dsr(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data)
{
	cyg_uint32 ch;
	float nrez;
	cyg_drv_interrupt_mask(vector);	// critical section ahead
	adcdata.svdcnt = adcdata.scancnt[adcdata.ig];
	for (ch = 0; ch < 8; ch++)
		adcdata.sumsvd[ch] = adcdata.sumadc[adcdata.ig][ch];
	adcdata.ig = ( adcdata.ig + 1) & 1;	// switch to next buffer
	cyg_drv_interrupt_unmask(vector);	// no longer critical
	nrez = ADRES / adcdata.svdcnt;
	for (ch = 0; ch < 8; ch++)	// compute
		adcdata.volt[ch] = nrez * adcdata.sumsvd[ch]; // converts to volt
	adcdata.scnt++;	// new reading available
} // end adc_dsr


// exported functions ==========================================================

cyg_uint32 GetADC( cyg_uint32 ch)
{
	cyg_uint32 result;
	// returns last available mean of ADC-readings from channel ch = [0..7]
	// ch == 8 returns adcdata.svdcnt, ch > 8 return sample-counter
	cyg_drv_dsr_lock();
	if (ch < 8) result = adcdata.sumsvd[ch];
	else if (ch == 8 ) result = adcdata.svdcnt;
	else result = adcdata.scnt;
	cyg_drv_dsr_unlock();
	return result;
}

float GetVolt(cyg_uint32 ch)
// returns mean of adc-reading converted to volts. ch must be in the range 0..7
// else a negative number (-1.0) is returned.
{
	float result;
	cyg_drv_dsr_lock();
	if (ch < 8)	result = adcdata.volt[ch];
	else result = -1.0;
	cyg_drv_dsr_unlock();
	return result;
} // end GetVolt

float GetSig(cyg_uint32 ch)
{
	// return physical parameter attached to ch=[0..7] in suitable units. The
	// evaluation uses the currently available mean value of the cor. channel.
	// Units - see above - just volts for now
	static const float c0 = 18.6;	// is heuristic - (R30 + R69) / R69
	static const float c1[2] = {-99.42, 196.63 / VREF}; // from old fw
	float result;
	cyg_drv_dsr_lock();
	switch (ch) {
	case 0: result = adcdata.volt[ch] * c0; break;		// Vpower
	case 1: result = adcdata.volt[ch] * c1[1] + c1[0]; break;	// Temperature
	case 2: result = 666.67 * adcdata.volt[ch]; break;	// I0 in mA
	case 3: result = 666.67 * adcdata.volt[ch]; break;	// I1 in mA
	case 4:; case 5:; case 6:;
	case 7: result = VREF - adcdata.volt[ch]; break;	// sun-sensor
	default:
		result = -1.0;
	} // switch ch
	cyg_drv_dsr_unlock();
	return result;
} // end GetSig

void GetSun(float *q)
{
	// returns voltages of the 4 quadrants as computed from last available means.
	int j, k;
	cyg_interrupt_disable();
	for ( j = 0; j < 4; j++) {
		q[j] = VREF - adcdata.volt[j+4];
		if (q[j] > 0.2)
			k = 0;
	} // end for j
	cyg_interrupt_enable();
}

#define MINSUN 0.5		// minimum level of sun

/* deviations of primary and secondary axis in app. encoder-counts
 * returns true if enough sun - sq is the mean of the 4 quadrants
 */
bool Read4Angle(double *p, double *s, double *qm)
{
	int j;
	float q[4];
	double sum;
	GetSun(q);
	sum = q[0];
	for (j = 1; j < 4; j++) sum += q[j];
	*qm = sum / 4.0;
	if (sum > MINSUN) {
		*p = ((q[0] + q[1]) - (q[2] + q[3])) / sum;
		*s = ((q[0] + q[3]) - (q[1] + q[2])) / sum;
		*p = (*p * SUN2RAD - eeram.sofs[0]) * RAD2EC;
		*s = (*s * SUN2RAD - eeram.sofs[1]) * RAD2EC;
		/* p is negative, if sun leads
		 * s is negative, if sun leads (sun higher than pointing)
		 */
		return true;
	} // if sum
	else {
		*p = 0; *s = 0;
		return false;
	} // end if sum else
}

void IniSun( cyg_uint32 linefreq )	// 50 or 60 allowed
{	cyg_uint32 reg;
	Iniihw();
	SetupADCdata();
// use TC2 to kick sampling at a rate of 1000 readings p. s. for each channel
    // enable peripheral clocks for TC2
    HAL_WRITE_UINT32(AT91_PMC + AT91_PMC_PCER,
    		AT91_PMC_PCER_TC2 | AT91_PMC_PCER_ADC );
    HAL_WRITE_UINT32(AT91C_BASE_TC2 + AT91_TC_BMR, 0); // do not care about XCn
    //configure TC2 to produce a pulse on TIOA2 every ms
    // sw-trigger and RC-match set TIOA, RA-match clears it.
    HAL_WRITE_UINT32(AT91C_BASE_TC2 + AT91_TC_CMR, AT91_TC_CMR_CLKS_MCK8 |
    		AT91_TC_CMR_CPCTRG | AT91_TC_CMR_WAVE | AT91_TC_CMR_ACPA_CLEAR |
    		AT91_TC_CMR_ACPC_SET | AT91_TC_CMR_ASWTRG_SET);
    //set RC for period and RA for pulse length
    if (linefreq == 60) linefreq = 5000; // 5/6 ms for 60 Hz lf
    else linefreq = 6000;		// 1 ms timing with 6 MHz clk for 50 Hz lf
    HAL_WRITE_UINT32(AT91C_BASE_TC2 + AT91_TC_RC, linefreq);	// clk is 6 MHz
    HAL_WRITE_UINT32(AT91C_BASE_TC2 + AT91_TC_RA, 3000); // app. 20% duty-cycle
	// TC2 now ready to go, but configure ad first

	// 5 MHz is maximum clock rate for 10-bit adc
#define MY_SHTIM (13 << 24)		// sample hold+conversion is 13+11=24
#define MY_STARTUP (7 << 16)	// I do not understand this parameter
#define MY_PRESCALE (23 << 8)	// MCK:48 MHz ==> AD-Clk is 1 MHz
#define MY_TRGEN 1				// trigger enable

    HAL_WRITE_UINT32(AT91_ADC + AT91_ADC_MR, MY_SHTIM | MY_STARTUP |
    		MY_PRESCALE | AT91_ADC_MR_TRGSEL_TIOA2 | MY_TRGEN); //
    HAL_WRITE_UINT32(AT91_ADC + AT91_ADC_CHER, 0xff);	// sample all 8 channels
    HAL_WRITE_UINT32(AT91_ADC + AT91_ADC_RPR, (cyg_uint32)&adcdata.adcbuf);
    HAL_WRITE_UINT32(AT91_ADC + AT91_ADC_RCR, DMACNT);
    // no set up an ISR for the ADC when the buffer with the 8 readings is in
    cyg_drv_interrupt_create( CYGNUM_HAL_INTERRUPT_ADC,
    		1,			// priority
    		(cyg_uint32)&adcdata,	// data required
    		&adc_isr,	// service routine
    		&adc_dsr,			// DSR required
    		&adc_handle,
    		&adc_int);	// storage area for isr
    cyg_drv_interrupt_attach( adc_handle);
    cyg_drv_interrupt_unmask( CYGNUM_HAL_INTERRUPT_ADC );

    HAL_WRITE_UINT32(AT91_ADC + AT91_ADC_IER, (1 << 19));	// RxBuff-IR

    HAL_WRITE_UINT32(AT91_ADC + AT91_ADC_PTCR, 1);	//enable transfer
	HAL_READ_UINT32(AT91_ADC + AT91_ADC_SR, reg );
    // start timer - this also sets TIOA2 and hence triggers a first reading
    HAL_WRITE_UINT32(AT91C_BASE_TC2 + AT91_TC_CCR, AT91_TC_CCR_CLKEN |
    		AT91_TC_CCR_TRIG); // sw-trigger&clk ena
} // end IniSun

#if SUN_TST & 1

	#include <stdio.h>
	#include <string.h>

	void Show(void )
	{
		char zeile[150];
		cyg_uint32 ch, err, cv, cmr, sr, chsr, imr, chsr2;
		if (showcnt == 0) {
			err = cyg_io_lookup( "/dev/tty1", &myio1 );
			sprintf(zeile,"\nsun %s at %s\n%4u", __DATE__, __TIME__, showcnt);
		}
		else {
			HAL_READ_UINT32(AT91C_BASE_TC2 + AT91_TC_CV, cv );
			HAL_READ_UINT32(AT91C_BASE_TC2 + AT91_TC_CMR, cmr );
			HAL_READ_UINT32(AT91C_BASE_TC2 + AT91_TC_SR, sr );
			HAL_READ_UINT32(AT91_ADC + AT91_ADC_SR, chsr );
			HAL_READ_UINT32(AT91_ADC + AT91_ADC_IMR, imr );
			HAL_READ_UINT32(AT91_ADC + AT91_ADC_SR, chsr2 );
			sprintf(zeile,"\n%4u cv:%6d cmr:%8x sr:%8x   chsr:%8x imr:%8x chsr:%8x",
					showcnt, cv, cmr, sr, chsr, imr, chsr2);
		}
		showcnt++;
		ch = strlen(zeile);
		cyg_io_write(myio1, zeile, &ch);
	} // end show
#endif
// EOF

[-- Attachment #3: sun.h --]
[-- Type: application/octet-stream, Size: 3512 bytes --]

#ifndef SUN_H_
#define SUN_H_
/*==============================================================================
System  :       INTRA S/W                                   Copyright 2008..
                ================================================================
                BRUSAG, Sensorik & messtechn.               ph: +41 44 926 74 74
                Entwicklungen,                              fx: +41 44 926 73 34
                Chapfwiesenstr. 14                          em: rbrusa@brusag.ch
                CH-8712 Staefa (Switzerland)                http://www.brusag.ch
================================================================================
SWSystem:	eCOS and toolchain arm-elf-gcc (GCC) 3.2.1 (eCosCentric)
Target:		INTRA Controller with AT91SAM7X-256
Abstract:	Sunsensor and low level handling of ADC of the AT91SAM7X.
	channel assignments are:
	0:	UPWR	VDC	DC power (24 VDCnom) from a voltage divider
	1:	UTEMP	°C	KTY13-6-based temperature sensor of board temperature
	2:	UCUR0	mA	current from base-shunt of motor0-driver	
	3:	UCUR1	mA	current from base-shunt of motor1-driver
	4:	q0		V	Signal from sun-sensor quadrant 0
	5:	q1		V	Signal from sun-sensor quadrant 1	
	4:	q2		V	Signal from sun-sensor quadrant 2
	7:	q3		V	Signal from sun-sensor quadrant 3
	
	This ADC-handler uses timer-counter 2 to trigger periodic sampling of all its 8
	channels. Data are stored in ram by dma-transfer. The interrupt routine and the
	associeted DSR implement higher level funktionality.

	Except for ch2 and 3, all all signals are slowly varying. ch2 and 3,
	are filtered with a 10k/100n=1 ms-RC-filter. Let's go for a 1 kHz sampling
	of all channels. We then take mean values sampled during 20 ms (50 Hz lines)
	At places with a 60 Hz line frequncy, the sampling is set for 5/6 ms.
	Irrespective of the lf, a full period consists of 20 readings.. We use TC2
	to produce periodic trigger events for the ADCs DMA.
	
	The ADC is read in an interrupt driven loop. We calculate means of all 8
	channels and these 8 readings are available by suitable function/routine
	calls.
--------------------------------------------------------------------------------
Edit history:
20-Oct-08 RWB:	Creation
*/
#include <cyg/infra/cyg_type.h>		// basic types for AT91-hardware
#include <cyg/hal/hal_io.h>			// registers and fields of AT91-hardware
//#include "ihw.h"

//#define AT91_PMC_PCER_ADC (1 << 17)	// still missing in cyg/hal/var_io.h

#define SUN_TST 0	// use bit-wize. 0 suppresses all tests

#if SUN_TST & 1
	extern void Show( void );
#endif

extern cyg_uint32 GetADC( cyg_uint32 ch);
// returns last available mean of ADC-readings from channel ch = [0..7]
// ch == 8 returns adcdata.svdcnt, ch > 8 return sample-counter

extern float GetVolt(cyg_uint32 ch);
// returns mean of adc-reading converted to volts. ch must be in the range 0..7

extern float GetSig(cyg_uint32 ch);
// return physical parameter attached to ch=[0..7] in suitable units. The
// evaluation uses the currently available mean value of the cor. channel.
// Units - see above

extern void GetSun(float *q);
// returns voltages of the 4 quadrants as computed from last available means.

extern bool Read4Angle(double *p, double *s, double *qm);
/* deviations of primary and secondary axis in app. encoder-counts
 * returns true if enough sun - qm is the mean of the 4 quadrants
 */

extern void IniSun(  cyg_uint32 linefreq );	// 50 or 60 allowed
//initializes TC2 and ADC for 1ms sampling on all 8 channels


#endif /*SUN_H_*/

[-- Attachment #4: Type: text/plain, Size: 148 bytes --]

-- 
Before posting, please read the FAQ: http://ecos.sourceware.org/fom/ecos
and search the list archive: http://ecos.sourceware.org/ml/ecos-discuss

RE: [ECOS] ARM7 ADC drivers - any progress?

[Steven Clugston]

> > Hi
> >
> > I want to use an ARM7 board running eCos for a battery
> charge monitor
> > /
> > UPS type application for which I need ADC support.
> >
> > I need a small and cheap standalone board for this and I have
> > identified
> > Olimex SAM7-MT-256 (AT91SAM7S256) and Olimex LPC-MT-2138 as
> possible
> > candidates.
> > Reading back through the archives there has been recent
> discussion about
> > an AT91 ADC driver and an LPC2xxx ADC driver modified from
> the LPC24xx
> > driver:
> >
> > AT91: http://sourceware.org/ml/ecos-discuss/2008-10/msg00018.html
> >
> > LPC2xxx: http://sourceware.org/ml/ecos-discuss/2008-12/msg00176.html
> >
> > Has there been any more progress with these?
> >
> > Are they likely to be contributed or made available anytime soon?
> >
> > Thanks,
> >
> > Steven
> >
> > --
> > Before posting, please read the FAQ:
> > http://ecos.sourceware.org/fom/ecos
> > and search the list archive:
> http://ecos.sourceware.org/ml/ecos-discuss
> >
> Hi Steven
> I am not familiar with the processors you mention, but I have
> written a
> module
> that uses the adc of the AT91SAM7X. Its not ready to go into
> ecos (as part
> of ecos), but it integrates smoothly into an ecos-based
> application - and
> it works. It may (or may not :-( ) be helpfull for you.
>
> Best regards
>    Robert

Looks interesting, if not a bit application specific, but from the comments it matches my application quite well.
I have battery voltage through a potential divider, a couple of motor currents off sense resitors and some hall effect sensors for other currents to measure.

Thanks,

Steven

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RE: [ECOS] ARM7 ADC drivers - any progress?

[Steven Clugston]

>> Hi Steven
>> I am not familiar with the processors you mention, but I have written a module that uses the adc of the AT91SAM7X. Its not ready to go into ecos (as part of ecos), but it integrates smoothly into an ecos-based application - and it works. It may (or may not :-( ) be helpfull for you.

>> Best regards
>>   Robert

Hi Robert

Thanks again for the SAM7 ADC code you posted. I've been trying to get this to work this week in the hope that I can use it as a staring point to writing a more generalised AT91 ADC driver and then post that for comments/review.

However, I've been struggling to get it to work on my AT91SAM7S256 (my own fault I'm sure).
After calling InitSun(), the TC2 timer seems to be kicking over ok as the timer counter register is incrementing, but I can't get the ADC unit to do any conversions. All of the settings you've used look reasonable, but even when the ADC is software triggered in a loop using the START bit ADC control reg, the status reg never changes and the ISR is never called.

I've trawlled the AT91SAM7 manual and can't find anything obvious (like an ADC clock - PMC is not an issue I think) that needs to be enabled for it to work, but clearly I've overlooked something as its not working.

Do you (or anyone else) have any ideas? Are there any imporant initialisation steps that's not included in the sun.c source?

Thanks for any insight.

Regards,

Steven

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Re: [ECOS] ARM7 ADC drivers - any progress?

[Robert Brusa]

[-- Attachment #1: Type: text/plain, Size: 550 bytes --]

Hi Steven
I do not know the AT91SAM7S, but assume its pretty the same ADC peripheral.

No, I can not think of anything why it should not work on your S-machine.  
But indeed (and for historical reasons) there is another init-routine in  
my system - see attachment. If it works with this, then check out what you  
really need of it :-) Lazy approach!

Another hint: Our board runs with an external 25 MHz clock and parameters  
are such to bring its main clock to 48 Mhz (done in configtool).

Hope this brings you one step further. Regards Robert


[-- Attachment #2: ihw.c --]
[-- Type: application/octet-stream, Size: 3603 bytes --]

/*==============================================================================
System  :       INTRA S/W                                   Copyright 2008..
                ================================================================
                BRUSAG, Sensorik & messtechn.               ph: +41 44 926 74 74
                Entwicklungen,                              fx: +41 44 926 73 34
                Chapfwiesenstr. 14                          em: rbrusa@brusag.ch
                CH-8712 Staefa (Switzerland)                http://www.brusag.ch
================================================================================
SWSystem:	eCOS and toolchain arm-elf-gcc (GCC) 3.2.1 (eCosCentric)
Target:		INTRA Controller with AT91SAM7X-256
Abstract:	Definitions for the INTRA-target und initialization routine
			for the ports and peripherals as used by the INTRA-target.
			See also /from_eva/PIOs_1.ods for more details.
--------------------------------------------------------------------------------
Edit history:
23-Sep-08 RWB:	Creation - based on Olis input
15-Okt-08 RWB:	clock for TC1 added

*/
// Board-Initialization routine. It configures pins as used by the INTRA-target.

//#include <cyg/infra/diag.h>
#include "ihw.h"

bool done = false;		//
cyg_uint32 mist;

void Iniihw( void )
{

	if ( done ) return;
	done = true;
	// enable peripheral clocks
    HAL_WRITE_UINT32(AT91_PMC + AT91_PMC_PCER, AT91_PMC_PCER_PWMC |
    		AT91_PMC_PCER_PIOA | AT91_PMC_PCER_PIOB);
//    HAL_WRITE_UINT32(AT91_PMC + AT91_PMC_PCER,        AT91_PMC_PCER_PIOA | AT91_PMC_PCER_PIOB);

#if PROTOB
    HAL_WRITE_UINT32(AT91C_BASE_PIOA + AT91_PIO_PPUDR,~0x00030000); //nicht pullup
    HAL_WRITE_UINT32(AT91C_BASE_PIOA + AT91_PIO_PPUER, 0x00030000); //pullup
#else
    HAL_WRITE_UINT32(AT91C_BASE_PIOA + AT91_PIO_PPUDR,~0x00000000); //nicht pullup
    HAL_WRITE_UINT32(AT91C_BASE_PIOA + AT91_PIO_PPUER, 0x00000000); //pullup
#endif
    // set output data register
    HAL_WRITE_UINT32(AT91C_BASE_PIOA + AT91_PIO_CODR, ~0x00000000); //out low
    HAL_WRITE_UINT32(AT91C_BASE_PIOA + AT91_PIO_SODR,  0x00000000); //out high
    // select output enable of PIO-controlled pins
    HAL_WRITE_UINT32(AT91C_BASE_PIOA + AT91_PIO_ODR,  ~0x4000080C); //PIO out dis
    HAL_WRITE_UINT32(AT91C_BASE_PIOA + AT91_PIO_OER,   0x4000080C); //PIO out ena
    // select peripheral a or b - actually all non-PIO on A are peripheral a
    HAL_WRITE_UINT32(AT91C_BASE_PIOA + AT91_PIO_ASR,   0x20071063); //peripherie A
//    HAL_WRITE_UINT32(AT91C_BASE_PIOA + AT91_PIO_BSR,   0x00000000); //peripherie B
    // select which goes out: PIO or peripheral a/b
    HAL_WRITE_UINT32(AT91C_BASE_PIOA + AT91_PIO_PDR,   0x20071063); //nicht PIO
    HAL_WRITE_UINT32(AT91C_BASE_PIOA + AT91_PIO_PER,  ~0x20071063); //PIO


    HAL_WRITE_UINT32(AT91C_BASE_PIOB + AT91_PIO_PPUDR,~0x00000000); //not pullup
    HAL_WRITE_UINT32(AT91C_BASE_PIOB + AT91_PIO_PPUER, 0x00000000); //pullup

    HAL_WRITE_UINT32(AT91C_BASE_PIOB + AT91_PIO_CODR,  0x00000000); //out low
    HAL_WRITE_UINT32(AT91C_BASE_PIOB + AT91_PIO_SODR,  0x00000000); //out high

    HAL_WRITE_UINT32(AT91C_BASE_PIOB + AT91_PIO_ODR,  ~0x00780000); //not out
    HAL_WRITE_UINT32(AT91C_BASE_PIOB + AT91_PIO_OER,   0x00780000); //OUT

    HAL_WRITE_UINT32(AT91C_BASE_PIOB + AT91_PIO_ASR,   0x02FBFFFF); //peripherie A
//    HAL_WRITE_UINT32(AT91C_BASE_PIOB + AT91_PIO_BSR,   0x00000000); //peripherie B

    HAL_WRITE_UINT32(AT91C_BASE_PIOB + AT91_PIO_PDR,   0x02FBFFFF); //nicht PIO
    HAL_WRITE_UINT32(AT91C_BASE_PIOB + AT91_PIO_PER,  ~0x02FBFFFF); //PIO

} // end Iniihw

[-- Attachment #3: ihw.h --]
[-- Type: application/octet-stream, Size: 8494 bytes --]

/*==============================================================================
System  :       INTRA S/W                                   Copyright 2008..
                ================================================================
                BRUSAG, Sensorik & messtechn.               ph: +41 44 926 74 74
                Entwicklungen,                              fx: +41 44 926 73 34
                Chapfwiesenstr. 14                          em: rbrusa@brusag.ch
                CH-8712 Staefa (Switzerland)                http://www.brusag.ch
================================================================================
SWSystem:	eCOS and toolchain arm-elf-gcc (GCC) 3.2.1 (eCosCentric)
Target:		INTRA Controller with AT91SAM7X-256
Abstract:	Definitions for the INTRA-target und initialization routine
			for the ports and peripherals as used by the INTRA-target.
			See also /from_eva/PIOs_1.ods for more details.
--------------------------------------------------------------------------------
Edit history:
23-Sep-08 RWB:	Creation - based on Olis input
13-Mar-09 RWB:	switch for prototype moved from rtc.c to this file.


*/

#ifndef BASE_H_
#define BASE_H_

#include <cyg/infra/cyg_type.h>
#include <cyg/hal/hal_io.h>

#define PROTOB 0	// set nonzero if running on a protoboard were SPI-in/out are tied tog


// *****************************************************************************
//				BASE ADDRESS DEFINITIONS FOR AT91SAM7S64 & AT91SAM7X
// rwb 080912   present status:
//              some of this is used for INTRA, but the list is not
//              checked and many definitions are probably even invalid
//     			for our maschine. See also <var_io.h> for more such definitions.
// *****************************************************************************
#define AT91C_BASE_SYSC           (0xFFFFF000) // (SYSC) Base Address
#define AT91C_BASE_AIC            (0xFFFFF000) // (AIC) Base Address
#define AT91C_BASE_DBGU           (0xFFFFF200) // (DBGU) Base Address
#define AT91C_BASE_PDC_DBGU       (0xFFFFF300) // (PDC_DBGU) Base Address
#define AT91C_BASE_PIOA           (0xFFFFF400) // (PIOA) Base Address
#define AT91C_BASE_PIOB           (0xFFFFF600) // (PIOB) Base Address
//#define AT91C_BASE_CKGR           (0xFFFFFC20) // (CKGR) Base Address
#define AT91C_BASE_PMC            (0xFFFFFC00) // (PMC) Base Address
#define AT91C_BASE_RSTC           (0xFFFFFD00) // (RSTC) Base Address
#define AT91C_BASE_RTTC           (0xFFFFFD20) // (RTTC) Base Address
#define AT91C_BASE_PITC           (0xFFFFFD30) // (PITC) Base Address
#define AT91C_BASE_WDTC           (0xFFFFFD40) // (WDTC) Base Address
#define AT91C_BASE_VREG           (0xFFFFFD60) // (VREG) Base Address
#define AT91C_BASE_MC             (0xFFFFFF00) // (MC) Base Address
#define AT91C_BASE_PDC_SPI        (0xFFFE0100) // (PDC_SPI) Base Address
#define AT91C_BASE_SPI            (0xFFFE0000) // (SPI) Base Address
#define AT91C_BASE_PDC_ADC        (0xFFFD8100) // (PDC_ADC) Base Address
#define AT91C_BASE_ADC            (0xFFFD8000) // (ADC) Base Address
#define AT91C_BASE_PDC_SSC        (0xFFFD4100) // (PDC_SSC) Base Address
#define AT91C_BASE_SSC            (0xFFFD4000) // (SSC) Base Address
#define AT91C_BASE_PDC_US1        (0xFFFC4100) // (PDC_US1) Base Address
#define AT91C_BASE_US1            (0xFFFC4000) // (US1) Base Address
#define AT91C_BASE_PDC_US0        (0xFFFC0100) // (PDC_US0) Base Address
#define AT91C_BASE_US0            (0xFFFC0000) // (US0) Base Address
#define AT91C_BASE_TWI            (0xFFFB8000) // (TWI) Base Address
#define AT91C_BASE_TC2            (0xFFFA0080) // (TC2) Base Address
#define AT91C_BASE_TC1            (0xFFFA0040) // (TC1) Base Address
#define AT91C_BASE_TC0            (0xFFFA0000) // (TC0) Base Address
#define AT91C_BASE_TCB            (0xFFFA0000) // (TCB) Base Address
#define AT91C_BASE_PWMC_CH3       (0xFFFCC260) // (PWMC_CH3) Base Address
#define AT91C_BASE_PWMC_CH2       (0xFFFCC240) // (PWMC_CH2) Base Address
#define AT91C_BASE_PWMC_CH1       (0xFFFCC220) // (PWMC_CH1) Base Address
#define AT91C_BASE_PWMC_CH0       (0xFFFCC200) // (PWMC_CH0) Base Address
#define AT91C_BASE_PWMC           (0xFFFCC000) // (PWMC) Base Address
#define AT91C_BASE_UDP            (0xFFFB0000) // (UDP) Base Address

#define AT91_PWMC_CMR        ( 0) // Channel Mode Register
#define AT91_PWMC_CDTYR      ( 4) // Channel Duty Cycle Register
#define AT91_PWMC_CPRDR      ( 8) // Channel Period Register
#define AT91_PWMC_CCNTR      (12) // Channel Counter Register
#define AT91_PWMC_CUPDR      (16) // Channel Update Register
#define AT91_PWMC_Reserved   (20) // Reserved
// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register --------
#define AT91C_PWMC_CPRE           (0xF <<  0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx
#define AT91C_PWMC_CPRE_MCK       (0x0) // (PWMC_CH)
#define AT91C_PWMC_CPRE_MCKA      (0xB) // (PWMC_CH)
#define AT91C_PWMC_CPRE_MCKB      (0xC) // (PWMC_CH)
#define AT91C_PWMC_CALG           (0x1 <<  8) // (PWMC_CH) Channel Alignment
#define AT91C_PWMC_CPOL           (0x1 <<  9) // (PWMC_CH) Channel Polarity
#define AT91C_PWMC_CPD            (0x1 << 10) // (PWMC_CH) Channel Update Period
// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register --------
#define AT91C_PWMC_CDTY           (0x0 <<  0) // (PWMC_CH) Channel Duty Cycle
// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register --------
#define AT91C_PWMC_CPRD           (0x0 <<  0) // (PWMC_CH) Channel Period
// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register --------
#define AT91C_PWMC_CCNT           (0x0 <<  0) // (PWMC_CH) Channel Counter
// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register --------
#define AT91C_PWMC_CUPD           (0x0 <<  0) // (PWMC_CH) Channel Update

// *****************************************************************************
// SOFTWARE API DEFINITION  FOR Pulse Width Modulation Controller Interface
// *****************************************************************************
// *** Register offset in AT91S_PWMC structure ***
#define AT91_PWMC_MR         ( 0) // PWMC Mode Register
#define AT91_PWMC_ENA        ( 4) // PWMC Enable Register
#define AT91_PWMC_DIS        ( 8) // PWMC Disable Register
#define AT91_PWMC_SR         (12) // PWMC Status Register
#define AT91_PWMC_IER        (16) // PWMC Interrupt Enable Register
#define AT91_PWMC_IDR        (20) // PWMC Interrupt Disable Register
#define AT91_PWMC_IMR        (24) // PWMC Interrupt Mask Register
#define AT91_PWMC_ISR        (28) // PWMC Interrupt Status Register
#define AT91_PWMC_VR         (252) // PWMC Version Register
#define AT91_PWMC_CH         (512) // PWMC Channel 0
// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register --------
#define AT91C_PWMC_DIVA           (0xFF <<  0) // (PWMC) CLKA divide factor.
#define AT91C_PWMC_PREA           (0xF <<  8) // (PWMC) Divider Input Clock Prescaler A
#define     AT91C_PWMC_PREA_MCK                  (0x0 <<  8) // (PWMC)
#define AT91C_PWMC_DIVB           (0xFF << 16) // (PWMC) CLKB divide factor.
#define AT91C_PWMC_PREB           (0xF << 24) // (PWMC) Divider Input Clock Prescaler B
#define     AT91C_PWMC_PREB_MCK                  (0x0 << 24) // (PWMC)
// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register --------
#define AT91C_PWMC_CHID0          (0x1 <<  0) // (PWMC) Channel ID 0
#define AT91C_PWMC_CHID1          (0x1 <<  1) // (PWMC) Channel ID 1
#define AT91C_PWMC_CHID2          (0x1 <<  2) // (PWMC) Channel ID 2
#define AT91C_PWMC_CHID3          (0x1 <<  3) // (PWMC) Channel ID 3
#define AT91C_PWMC_CHID4          (0x1 <<  4) // (PWMC) Channel ID 4
#define AT91C_PWMC_CHID5          (0x1 <<  5) // (PWMC) Channel ID 5
#define AT91C_PWMC_CHID6          (0x1 <<  6) // (PWMC) Channel ID 6
#define AT91C_PWMC_CHID7          (0x1 <<  7) // (PWMC) Channel ID 7


#define AT91C_BASE_PWMC_CH3       (0xFFFCC260) // (PWMC_CH3) Base Address
#define AT91C_BASE_PWMC_CH2       (0xFFFCC240) // (PWMC_CH2) Base Address
#define AT91C_BASE_PWMC_CH1       (0xFFFCC220) // (PWMC_CH1) Base Address
#define AT91C_BASE_PWMC_CH0       (0xFFFCC200) // (PWMC_CH0) Base Address
#define AT91C_BASE_PWMC           (0xFFFCC000) // (PWMC) Base Address

// external routines / prototypes ==============================================

extern void Iniihw( void );	// initialization routine -flag-protected, may be
							// called more than once.

#endif /*BASE_H_*/

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RE: [ECOS] ARM7 ADC drivers - any progress?

[Steven Clugston]

>> Hi Steven
>> I do not know the AT91SAM7S, but assume its pretty the same ADC peripheral.

>> No, I can not think of anything why it should not work on your S-machine.
>> But indeed (and for historical reasons) there is another init-routine in my system - see attachment. If it works with this, then check out what you really need of it :-) Lazy approach!

>> Another hint: Our board runs with an external 25 MHz clock and parameters are such to bring its main clock to 48 Mhz (done in configtool).

>> Hope this brings you one step further. Regards Robert

Thanks for the additional code Robert.

I chased it through from just taking single shot software triggered samples with no DMA and in the end, just changing the code from TC2 to TC1 made it work. For some reason just enabling HW triggering and setting it to TC2 stops the ADC from returning any results. I've not had chance to find out why yet, but I'm not sure which TC is being used for the system timer. I had assumed it was TC0, but if it is TC2, then this might explain a few things.

I'm slightly confused by a couple of things, perhaps someone who is familiar with the AT91 hal code might be able to clearup.

In hal/arm/at91/at91sam7s/current/src/at91sam7s_misc.c:

#ifdef CYGBLD_HAL_ARM_AT91_TIMER_TC
  /* Enable peripheral clocks for TC 0 and 1 if they are to be used */
  HAL_WRITE_UINT32(AT91_PMC+AT91_PMC_PCER,
                   AT91_PMC_PCER_TC0 |
                   AT91_PMC_PCER_TC2);
#endif

The above only enbles the clocks, so is not the cause of my problem, but the comment seems to contradict the statement below it. Should TC1 or TC2 be enabled here?

Also in hal/arm/at91/var/current/src/timer_tc.c:

void hal_delay_us(cyg_int32 usecs)
{
    cyg_uint32 stat;
    cyg_uint64 ticks;
#if defined(CYGHWR_HAL_ARM_AT91_JTST)
    // TC2 is reserved for AD/DA. Use TC1 instead.
    CYG_ADDRESS timer = AT91_TC+AT91_TC_TC1;
#else
    CYG_ADDRESS timer = AT91_TC+AT91_TC_TC2;
#endif

What is CYGHWR_HAL_ARM_AT91_JTST ? I can't find anything in CDL for it. If it is not being defined, then this answers my question about which timer is being used for the system clock.

Thanks,

Steven

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Re: [ECOS] ARM7 ADC drivers - any progress?

[Andrew Lunn]

> I'm slightly confused by a couple of things, perhaps someone who is
> familiar with the AT91 hal code might be able to clearup.

The HAL can get its tick from two different sources. Some devices, ag
the AT91SAM, have a PIT, programmable Interrupt Timer. All AT91 have
TC, Timer Counter. There is a CDL option to control which is used.

    Andrew

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RE: [ECOS] ARM7 ADC drivers - any progress?

[Steven Clugston]

>> I'm slightly confused by a couple of things, perhaps someone who is
>> familiar with the AT91 hal code might be able to clearup.

> The HAL can get its tick from two different sources. Some devices, ag
> the AT91SAM, have a PIT, programmable Interrupt Timer. All AT91 have
> TC, Timer Counter. There is a CDL option to control which is used.

>    Andrew

Thanks for pointing this out Andrew, but as the Timer Counter is enabled by default, I was trying to clear up which TC should be used for what (by AT91 hal convention).
There is a comment somewhere in the code stating that TC2 should be reserved for ADC/DAC use and Robert has used it with his ADC code, yet it appears to be in use by the system timer when the PIT CDL option has not been explicitly set.

Is it fair to say that the PIT is conventionally used for the system timer when available and hence it is OK to use TC2 as a default for an AT91(SAM) ADC driver?

If so then would it be reasonable to have a cdl entry for the ADC driver like:

requires CYGNUM_HAL_INTERRUPT_PITC

Or is that constraint too restrictive for an AT91 platform wide ADC driver as not all variants have a PIT?

Steven

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Re: [ECOS] ARM7 ADC drivers - any progress?

[Bob Brusa]

Am 01.09.2009, 11:50 Uhr, schrieb Andrew Lunn <andrew@lunn.ch>:

>> I'm slightly confused by a couple of things, perhaps someone who is
>> familiar with the AT91 hal code might be able to clearup.
>
> The HAL can get its tick from two different sources. Some devices, ag
> the AT91SAM, have a PIT, programmable Interrupt Timer. All AT91 have
> TC, Timer Counter. There is a CDL option to control which is used.
>
>     Andrew
>
Steven
in fact: our boards are configured to use PIT as system clock. This may  
explain some, if not all? of your problems.
    Robert


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