From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 29455 invoked by alias); 25 Aug 2011 10:38:20 -0000 Received: (qmail 29447 invoked by uid 22791); 25 Aug 2011 10:38:19 -0000 X-SWARE-Spam-Status: No, hits=-0.8 required=5.0 tests=AWL,BAYES_00,RCVD_IN_DNSWL_NONE X-Spam-Check-By: sourceware.org Received: from anchor-post-1.mail.demon.net (HELO anchor-post-1.mail.demon.net) (195.173.77.132) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Thu, 25 Aug 2011 10:37:51 +0000 Received: from calivar.demon.co.uk ([83.104.54.243] helo=calivar.com) by anchor-post-1.mail.demon.net with esmtp (Exim 4.69) id 1QwXJl-0001Be-iM for ecos-discuss@ecos.sourceware.org; Thu, 25 Aug 2011 10:37:49 +0000 Received: from [10.0.1.1] (daikon.calivar.com [10.0.1.1]) (using TLSv1 with cipher DHE-RSA-CAMELLIA256-SHA (256/256 bits)) (No client certificate requested) by calivar.com (Postfix) with ESMTPS id AF66319F751 for ; Thu, 25 Aug 2011 11:37:48 +0100 (BST) Message-ID: <4E5625FC.2030803@calivar.com> Date: Thu, 25 Aug 2011 10:38:00 -0000 From: Nick Garnett User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-GB; rv:1.9.2.18) Gecko/20110616 SUSE/3.1.11 Thunderbird/3.1.11 MIME-Version: 1.0 To: ecos-discuss@ecos.sourceware.org References: <20110824103404.51600@gmx.net> <20110824141051.115980@gmx.net> <20110824145744.116000@gmx.net> <20110825084845.184240@gmx.net> In-Reply-To: <20110825084845.184240@gmx.net> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Mailing-List: contact ecos-discuss-help@ecos.sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: ecos-discuss-owner@ecos.sourceware.org Subject: Re: [ECOS] ecos-3.0 current stm32 bug? X-SW-Source: 2011-08/txt/msg00054.txt.bz2 On 25/08/11 09:48, Philipp Meier wrote: > Hello Christophe > > it is the SWI instruction ("svc 0" in disassem code) that triggers the exception (therefore breakpoint in hal_switch_state_vsr is never reached). > > Where does the SWI instruction get's it's information about where to jump to? Is it the hal_vsr_table (located at 0x20000000)? In entry 11 I have 0x8040025 which is the address for hal_switch_state_vsr - and yet it does not jumps to 0x8040025 but instead to 0x8040042 (hal_default_exception_vsr). > > Any idea about the reason for this behaviour? The SWI is probably causing the CPU to take a HardFault exception because BASEPRI is higher than the priority of the SWI exception. If I understand correctly, both your bootloader and application are configured for ROM startup. The ROM startup code in hal_misc.c expects to find the CPU in its initial state. When your application runs, the bootloader has already run this code and put it into a different state, which will then cause the SWI to throw a HardFault. For your application you really need a new startup type that does the RAM initialization parts of a ROM startup, but omits parts of the hardware initialization. -- Nick Garnett eCos Kernel Architect eCosCentric Limited http://www.eCosCentric.com The eCos experts Barnwell House, Barnwell Drive, Cambridge, UK. Tel: +44 1223 245571 Registered in England and Wales: Reg No: 4422071 -- Before posting, please read the FAQ: http://ecos.sourceware.org/fom/ecos and search the list archive: http://ecos.sourceware.org/ml/ecos-discuss