From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 16372 invoked by alias); 25 Aug 2011 11:25:27 -0000 Received: (qmail 16346 invoked by uid 22791); 25 Aug 2011 11:25:26 -0000 X-SWARE-Spam-Status: No, hits=-1.5 required=5.0 tests=AWL,BAYES_00,FREEMAIL_FROM,RCVD_IN_DNSWL_NONE,T_TO_NO_BRKTS_FREEMAIL X-Spam-Check-By: sourceware.org Received: from mailout-de.gmx.net (HELO mailout-de.gmx.net) (213.165.64.23) by sourceware.org (qpsmtpd/0.43rc1) with SMTP; Thu, 25 Aug 2011 11:25:11 +0000 Received: (qmail invoked by alias); 25 Aug 2011 11:25:09 -0000 Received: from mail.neratec.ch (EHLO [192.168.11.84]) [80.75.119.105] by mail.gmx.net (mp055) with SMTP; 25 Aug 2011 13:25:09 +0200 Message-ID: <4E563112.9060608@gmx.ch> Date: Thu, 25 Aug 2011 11:25:00 -0000 From: Philipp Meier User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.9.2.18) Gecko/20110617 Thunderbird/3.1.11 MIME-Version: 1.0 To: ecos-discuss@ecos.sourceware.org References: <20110824103404.51600@gmx.net> <20110824141051.115980@gmx.net> <20110824145744.116000@gmx.net> <20110825084845.184240@gmx.net> <4E5625FC.2030803@calivar.com> In-Reply-To: <4E5625FC.2030803@calivar.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-IsSubscribed: yes Mailing-List: contact ecos-discuss-help@ecos.sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: ecos-discuss-owner@ecos.sourceware.org Subject: Re: [ECOS] ecos-3.0 current stm32 bug? X-SW-Source: 2011-08/txt/msg00055.txt.bz2 On 08/25/2011 12:37 PM, Nick Garnett wrote: > On 25/08/11 09:48, Philipp Meier wrote: >> Hello Christophe >> >> it is the SWI instruction ("svc 0" in disassem code) that triggers the exception (therefore breakpoint in hal_switch_state_vsr is never reached). >> >> Where does the SWI instruction get's it's information about where to jump to? Is it the hal_vsr_table (located at 0x20000000)? In entry 11 I have 0x8040025 which is the address for hal_switch_state_vsr - and yet it does not jumps to 0x8040025 but instead to 0x8040042 (hal_default_exception_vsr). >> >> Any idea about the reason for this behaviour? > The SWI is probably causing the CPU to take a HardFault exception > because BASEPRI is higher than the priority of the SWI exception. > > If I understand correctly, both your bootloader and application are > configured for ROM startup. The ROM startup code in hal_misc.c expects > to find the CPU in its initial state. When your application runs, the > bootloader has already run this code and put it into a different state, > which will then cause the SWI to throw a HardFault. > > For your application you really need a new startup type that does the > RAM initialization parts of a ROM startup, but omits parts of the > hardware initialization. > > Sound logic but: Why would the code built under cygwin run (same architecture with bootloader and application) but not work when built under Linux? On both OS I use the same version of the arm-eabi tools. On both OS I use the same ecos library (ecos-3.0) and the same source code for bootloader/application. Any idea about what would make the difference? -- Before posting, please read the FAQ: http://ecos.sourceware.org/fom/ecos and search the list archive: http://ecos.sourceware.org/ml/ecos-discuss