From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 10636 invoked by alias); 22 May 2012 18:01:58 -0000 Received: (qmail 10623 invoked by uid 22791); 22 May 2012 18:01:56 -0000 X-SWARE-Spam-Status: No, hits=-1.8 required=5.0 tests=AWL,BAYES_00 X-Spam-Check-By: sourceware.org Received: from relay03.alfahosting-server.de (HELO relay03.alfahosting-server.de) (80.86.191.79) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Tue, 22 May 2012 18:01:43 +0000 Received: by relay03.alfahosting-server.de (Postfix, from userid 1001) id D3B8532C057B; Tue, 22 May 2012 20:01:40 +0200 (CEST) X-Spam-DCC: : Received: from alfa3018.alfahosting-server.de (alfa3018.alfahosting-server.de [109.237.140.30]) by relay03.alfahosting-server.de (Postfix) with ESMTP id 70C2932C031D for ; Tue, 22 May 2012 20:01:38 +0200 (CEST) Received: from pc.martinlaabs.de (p54B355C5.dip.t-dialin.net [84.179.85.197]) by alfa3018.alfahosting-server.de (Postfix) with ESMTPSA id 44B4B515C43B for ; Tue, 22 May 2012 20:01:37 +0200 (CEST) Message-ID: <4FBBD47E.3060501@mailbox.tu-dresden.de> Date: Tue, 22 May 2012 18:01:00 -0000 From: Martin Laabs User-Agent: Mozilla/5.0 (X11; FreeBSD amd64; rv:10.0.3) Gecko/20120329 Thunderbird/10.0.3 MIME-Version: 1.0 To: eCos Discuss Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Virus-Checker-Version: clamassassin 1.2.4 with ClamAV 0.97.3/14946/Tue May 22 15:45:25 2012 X-IsSubscribed: yes Mailing-List: contact ecos-discuss-help@ecos.sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: ecos-discuss-owner@ecos.sourceware.org Subject: [ECOS] DSR interruptible by scheduler + memory barriers X-SW-Source: 2012-05/txt/msg00015.txt.bz2 Hello, unfortunately I couldn't find the answer in the documentation. If the scheduler runs a DSR. Can this DSR become interrupted by an other thread or another DSR? (Of cause an ISR can interrupt it) The background is that I wanna share data between a thread an a DSR and want to know whether I have to call cyg_(un)lock_scheduler when changing the data. And another question about that - how are memory barriers implemented in eCos? (Are they implemented at all?) Background: I have - for example - a status bit field that is copied to a (ISR/DSR) shared variable in the ISR. Now - if the compiler decides to put this variable into a register (in the ISR function) the DSR will get the wrong data. I could of cause declare the variable as volatile but this might be a performance issue in other cases where more data is affected. Best regards, Martin Laabs -- Before posting, please read the FAQ: http://ecos.sourceware.org/fom/ecos and search the list archive: http://ecos.sourceware.org/ml/ecos-discuss