From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 3755 invoked by alias); 31 Mar 2013 12:06:09 -0000 Mailing-List: contact ecos-discuss-help@ecos.sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: ecos-discuss-owner@ecos.sourceware.org Received: (qmail 3706 invoked by uid 89); 31 Mar 2013 12:06:02 -0000 X-Spam-SWARE-Status: No, score=-3.6 required=5.0 tests=AWL,BAYES_00,KHOP_THREADED,RP_MATCHES_RCVD,SPF_HELO_PASS autolearn=ham version=3.3.1 Received: from www.meduna.org (HELO meduna.org) (92.240.244.38) by sourceware.org (qpsmtpd/0.84/v0.84-167-ge50287c) with ESMTP; Sun, 31 Mar 2013 12:05:59 +0000 Received: from dial-95-105-165-4-orange.orange.sk ([95.105.165.4] helo=[192.168.130.22]) by meduna.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1UMH1E-0002NX-7t; Sun, 31 Mar 2013 14:05:53 +0200 Message-ID: <5158269C.5000804@meduna.org> Date: Sun, 31 Mar 2013 12:06:00 -0000 From: Stanislav Meduna User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:17.0) Gecko/20130307 Thunderbird/17.0.4 MIME-Version: 1.0 To: randyqiuxy CC: eCos Discussion References: , <51546EFC.5050603@dallaway.org.uk> In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Authenticated-User: stano@meduna.org X-Authenticator: dovecot_plain X-Spam-Score: -6.9 X-Spam-Score-Int: -68 X-Exim-Version: 4.72 (build at 25-Oct-2012 18:35:58) X-Date: 2013-03-31 14:05:53 X-Connected-IP: 95.105.165.4:2127 X-Message-Linecount: 32 X-Body-Linecount: 17 X-Message-Size: 1333 X-Body-Size: 576 X-Received-Count: 1 X-Recipient-Count: 2 X-Local-Recipient-Count: 2 X-Local-Recipient-Defer-Count: 0 X-Local-Recipient-Fail-Count: 0 Subject: Re: [ECOS] why should ISR arrange that the same interrupt would not recur until DSR completed? X-SW-Source: 2013-03/txt/msg00071.txt.bz2 On 31.03.2013 10:10, Randy wrote: > But why? If other interrupt could be enable when processing DSR, why > is the same interrupt not allowed? 1) Other interrupt does not need to synchronize access to the hardware and/or data structures shared between the ISR and corresponding DSR. Remember, neither the ISR nor DSR can block. Disabling interrupts outside of interrupt handlers is generally frowned upon. 2) The list of pending DSRs is now upper bounded. With the same interrupt enabled it would become unbounded. Regards -- Stano -- Before posting, please read the FAQ: http://ecos.sourceware.org/fom/ecos and search the list archive: http://ecos.sourceware.org/ml/ecos-discuss