From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 15738 invoked by alias); 7 Apr 2013 13:21:59 -0000 Mailing-List: contact ecos-discuss-help@ecos.sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: ecos-discuss-owner@ecos.sourceware.org Received: (qmail 15725 invoked by uid 89); 7 Apr 2013 13:21:59 -0000 X-Spam-SWARE-Status: No, score=-4.4 required=5.0 tests=AWL,BAYES_00,KHOP_THREADED,RP_MATCHES_RCVD,SPF_HELO_PASS autolearn=ham version=3.3.1 Received: from www.meduna.org (HELO meduna.org) (92.240.244.38) by sourceware.org (qpsmtpd/0.84/v0.84-167-ge50287c) with ESMTP; Sun, 07 Apr 2013 13:21:51 +0000 Received: from dial-95-105-165-4-orange.orange.sk ([95.105.165.4] helo=[192.168.130.22]) by meduna.org with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1UOpXU-0007cm-Qe; Sun, 07 Apr 2013 15:21:47 +0200 Message-ID: <516172E4.6080207@meduna.org> Date: Sun, 07 Apr 2013 13:21:00 -0000 From: Stanislav Meduna User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:17.0) Gecko/20130328 Thunderbird/17.0.5 MIME-Version: 1.0 To: randyqiuxy CC: eCos Discussion References: , <51546EFC.5050603@dallaway.org.uk> , <5158269C.5000804@meduna.org> , <51597647.1010803@meduna.org> In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Authenticated-User: stano@meduna.org X-Authenticator: dovecot_plain X-Spam-Score: -6.9 X-Spam-Score-Int: -68 X-Exim-Version: 4.72 (build at 25-Oct-2012 18:35:58) X-Date: 2013-04-07 15:21:47 X-Connected-IP: 95.105.165.4:2928 X-Message-Linecount: 46 X-Body-Linecount: 31 X-Message-Size: 2088 X-Body-Size: 1171 X-Received-Count: 1 X-Recipient-Count: 2 X-Local-Recipient-Count: 2 X-Local-Recipient-Defer-Count: 0 X-Local-Recipient-Fail-Count: 0 Subject: Re: [ECOS] why should ISR arrange that the same interrupt would not recur until DSR completed? X-SW-Source: 2013-04/txt/msg00010.txt.bz2 On 07.04.2013 14:06, Randy wrote: > After one ISR is over, the DSRs in FIFO queue starts to run one by > one like A=>B=>C=>... If one interrupt comes when B is running, then > what will happen? If B is stoped and the new ISR is going to run, > then, how and when does the B come back(we may cann't use > "reschedule" to describe it)? The processor detects the interrupt, saves the current program counter on the stack, looks up the table defining wich handler is to be run for tha particular interupt source and runs the handler. When this handler returns, then whatever the handler interrupted will continue where it was interrupted, in this case B. The exact sequence of steps is hardware- and configuration-dependent, the interrupt and exception handling is where the architectures differ significantly. > Or, could you tell me which code snippet in eCos3.0 shows the handler? This is architecture specific partly assembler code. Look for vectors.S and other files in your HAL, but you will only understand it if you have quite detailed knowledge about your processor. I never needed to go that deep. Regards -- Stano -- Before posting, please read the FAQ: http://ecos.sourceware.org/fom/ecos and search the list archive: http://ecos.sourceware.org/ml/ecos-discuss