From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 32465 invoked by alias); 1 Nov 2013 17:11:23 -0000 Mailing-List: contact ecos-discuss-help@ecos.sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: ecos-discuss-owner@ecos.sourceware.org Received: (qmail 32450 invoked by uid 89); 1 Nov 2013 17:11:22 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.9 required=5.0 tests=AWL,BAYES_00,SPF_HELO_PASS,SPF_PASS autolearn=ham version=3.3.2 X-HELO: calivar.com Received: from calivar.demon.co.uk (HELO calivar.com) (83.104.54.243) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES256-SHA encrypted) ESMTPS; Fri, 01 Nov 2013 17:11:21 +0000 Received: from daikon.calivar.com (daikon.calivar.com [10.0.1.1]) (using TLSv1 with cipher ECDHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by calivar.com (Postfix) with ESMTPS id 3427B71609; Fri, 1 Nov 2013 17:11:18 +0000 (GMT) Message-ID: <5273E0B5.4090000@calivar.com> Date: Fri, 01 Nov 2013 17:11:00 -0000 From: Nick Garnett User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:24.0) Gecko/20100101 Thunderbird/24.0 MIME-Version: 1.0 To: Andrew Parlane , ecos-discuss@ecos.sourceware.org References: <5273D735.8060505@carallon.com> In-Reply-To: <5273D735.8060505@carallon.com> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-IsSubscribed: yes Subject: Re: [ECOS] interrupts disabled during DSRs on ARM X-SW-Source: 2013-11/txt/msg00004.txt.bz2 On 01/11/13 16:30, Andrew Parlane wrote: > Hi, > > Another question regarding the ARM interrupt handling code. > > When an IRQ occurs we jump to IRQ: in hal\arm\arch\current\src\vectors.s > we save the previous state, potentially switch stack, take the scheduler > lock, find the IRQ number, call the ISR, and then call interrupt_end. > > interrupt_end() in kernel\current\src\intr\intr.cxx queues up the DSR if > asked to, and then unlocks the scheduler. As long as the scheduler > wasn't locked before the IRQ, this causes the scheduler to call any DSRs > that are queued up. This happens in call_pending_DSRs_inner() in the > same file. We disable interrupts, get the pointer to the DSR to call, > restore interrupts and call the DSR. > > In the case I've been describing we are still in the IRQ handler, and as > such the interrupts are disabled throughout the entirety of this, and > hence disabled in the DSR. > > Looking at: http://ecos.sourceware.org/docs-1.3.1/ref/ecos-ref.c.html in > the first paragraph it states: "This separation explicitly allows for > the DSRs to be run with interrupts enabled, thus allowing other > potentially higher priority interrupts to occur and be processed while > processing a lower priority interrupt." > > Am I missing something here? call_pending_DSRs_inner() is called via cyg_interrupt_call_pending_DSRs() which is itself called by hal_interrupt_stack_call_pending_DSRs() in vectors.S. This last routine switches to the interrupt stack and enables interrupts before calling cyg_interrupt_call_pending_DSRs(). -- Nick Garnett Kernel Architect eCosCentric Limited http://www.eCosCentric.com The eCos experts Barnwell House, Barnwell Drive, Cambridge, UK. Tel: +44 1223 245571 Registered in England and Wales: Reg No: 4422071 -- Before posting, please read the FAQ: http://ecos.sourceware.org/fom/ecos and search the list archive: http://ecos.sourceware.org/ml/ecos-discuss