[ECOS] The Alignment and Init of Ethernet Data Structures

[ECOS] The Alignment and Init of Ethernet Data Structures

[Les Miklosy]

This question regards the Ethernet drivers found in the devs/eth 
directory. I found the data structure for xxx_eth_info in these header 
files: fec.h, fcc.h, quicc_eth.h, ppc405_eth.h. Moab uses the 
ppc405_eth.h while Rattler uses the fcc.h. When the data structure 
xxx_eth_info is initialized, the Moab and Rattler configurations use 
data alignment constructs (the literature calls 'compound literals')  
while fec and quicc_eth do not. An example of the data alignment 
construct for Moab is:

    // Align buffers on a cache boundary
    #define RxBUFSIZE
    CYGNUM_DEVS_ETH_POWERPC_PPC405_RxNUM*CYGNUM_DEVS_ETH_POWERPC_PPC405_BUFSIZE
    #define TxBUFSIZE
    CYGNUM_DEVS_ETH_POWERPC_PPC405_TxNUM*CYGNUM_DEVS_ETH_POWERPC_PPC405_BUFSIZE
    static unsigned char ppc405_eth_rxbufs[RxBUFSIZE]
    __attribute__((aligned(HAL_DCACHE_LINE_SIZE)));
    static unsigned char ppc405_eth_txbufs[TxBUFSIZE]
    __attribute__((aligned(HAL_DCACHE_LINE_SIZE)));
    static mal_bd_t
    ppc405_eth_rxbd[CYGNUM_DEVS_ETH_POWERPC_PPC405_RxNUM]
    __attribute__((aligned(HAL_DCACHE_LINE_SIZE)));
    static mal_bd_t
    ppc405_eth_txbd[CYGNUM_DEVS_ETH_POWERPC_PPC405_TxNUM]
    __attribute__((aligned(HAL_DCACHE_LINE_SIZE)));


Why are these used in the cases of fcc and ppc405 but not for fec and 
quicc? Is the alignment necessary or recommended for new ports? What 
might be the consequences if alignment during initialization is not 
used? For other platforms are we relying on the compiler to 
rack-and-stack data structures properly on boundaries optimized by the 
compiler?

Thanks for any guidance.
Les







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