From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 4626 invoked by alias); 23 Aug 2012 14:14:40 -0000 Received: (qmail 4616 invoked by uid 22791); 23 Aug 2012 14:14:39 -0000 X-SWARE-Spam-Status: No, hits=4.4 required=5.0 tests=AWL,BAYES_50,RCVD_IN_HOSTKARMA_YE,SARE_PROLOSTOCK_SYM3 X-Spam-Check-By: sourceware.org Received: from mail136.messagelabs.com (HELO mail136.messagelabs.com) (216.82.249.3) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Thu, 23 Aug 2012 14:14:19 +0000 X-Env-Sender: Richard.Morris@lifetech.com X-Msg-Ref: server-8.tower-136.messagelabs.com!1345731209!3953585!1 X-StarScan-Received: X-StarScan-Version: 6.6.1.3; banners=-,-,- X-VirusChecked: Checked Received: (qmail 24312 invoked from network); 23 Aug 2012 14:13:30 -0000 Received: from unknown (HELO cbd01exc7ets01.ads.invitrogen.net) (198.160.190.35) by server-8.tower-136.messagelabs.com with RC4-SHA encrypted SMTP; 23 Aug 2012 14:13:30 -0000 Received: from CBD01EXC7HTCA02.ads.invitrogen.net (10.33.67.51) by cbd01exc7ets01.ads.invitrogen.net (172.16.16.35) with Microsoft SMTP Server (TLS) id 8.3.192.1; Thu, 23 Aug 2012 06:26:36 -0700 Received: from CBD01MAIL02.ads.invitrogen.net ([10.33.67.57]) by CBD01EXC7HTCA02.ads.invitrogen.net ([10.33.67.51]) with mapi; Thu, 23 Aug 2012 07:13:29 -0700 From: "Morris, Richard" To: eCos Discussion Date: Thu, 23 Aug 2012 14:14:00 -0000 Message-ID: <883A4093-5FE8-4B3E-9460-8DDFF1DBB115@lifetech.com> Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-IsSubscribed: yes Mailing-List: contact ecos-discuss-help@ecos.sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: ecos-discuss-owner@ecos.sourceware.org Subject: [ECOS] Re: STM32F4 timers test problem X-SW-Source: 2012-08/txt/msg00005.txt.bz2 Additional information: Just enabling the clocks in the APB for the timers doesn't resolve the issu= e as it appeared below. I commented out the init_timer() function that act= ually starts the timers and the exception still occurs. It seems to have something to do with some of the timers running. If I sta= rt only timer 8 in the timers.c test, the exception still occurs. However,= if I start timer 7, or 6, or 5 the exception seems to not occur, or at lea= st the frequency is low enough that it isn't seen during the interval of th= e test. Curiously if I build the tests using the JTAG startup type rather than ROM,= the test will fail after 10+ loops with a"Stack base corrupt" exception. = When built for ROM startup type, the test will run for at least 500 loops. <<<<<<<<<<<<<<<<<<<<<<<<<<<< PREVIOUS POST BEGIN >>>>>>>>>>>>>>>>>>>>>>>>>>= >>>>>>>>>>>>>>>>>>>> I have been having trouble running the STM32F4 timers test on the STM3240G-= Eval board: ecos/packages/hal/cortexm/stm32/var/current/tests/timers.c The test would SIGTRAP in GDB when executing: cyg_thread_delay( 5*100 ); in the while loop in "timers_test()" in timers.c. The issue seems to be that the clocks for the timers are not enabled in the= RCC_APB1ENR and=20 RCC_APB2ENR registers, so when the timers are attempted to be initialized, = the initialization is not successful and the timers don't run. I am not exactly sure why this would relate to the SIGTRAP, but when I reso= lved the timer initialization, the SIGTRAP went away. If anyone could expl= ain this, I would be interested in better understanding. I enabled these clocks (now the test seems to run reliably) by adding code = shown below at the end of "hal_variant_init()" in stm32_misc.c to initializ= e the TIMer clocks. I suspect this is not the correct place for this change, but wasn't sure wh= ere to make it. There probably also needs to be some conditional compilati= on to take care of the various variants of the processor. ###########################################################################= ############ void hal_variant_init( void ) { #if 1 //!defined(CYG_HAL_STARTUP_RAM) hal_start_clocks(); #endif // Attach EXTI springboard to interrupt vectors HAL_INTERRUPT_ATTACH( CYGNUM_HAL_INTERRUPT_EXTI9_5, hal_exti_isr, 0, 0= ); HAL_INTERRUPT_ATTACH( CYGNUM_HAL_INTERRUPT_EXTI15_10, hal_exti_isr, 0, 0= ); #ifdef CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT hal_if_init(); #endif #if (1) // A hack for now, enable timer clocks for STM32F407IG unsigned int reg; HAL_READ_UINT32((CYGHWR_HAL_STM32_RCC + CYGHWR_HAL_STM32_RCC_APB1ENR), r= eg ); HAL_WRITE_UINT32((CYGHWR_HAL_STM32_RCC + CYGHWR_HAL_STM32_RCC_APB1ENR), (reg | (1u << CYGHWR_HAL_STM32_RCC_APB1ENR_TIM2)=20 | (1u << CYGHWR_HAL_STM32_RCC_APB1ENR_TIM3) | (1u << CYGHWR_HAL_STM32_RCC_APB1ENR_TIM4) | (1u << CYGHWR_HAL_STM32_RCC_APB1ENR_TIM5) | (1u << CYGHWR_HAL_STM32_RCC_APB1ENR_TIM6) | (1u << CYGHWR_HAL_STM32_RCC_APB1ENR_TIM7) ) ); HAL_READ_UINT32((CYGHWR_HAL_STM32_RCC + CYGHWR_HAL_STM32_RCC_APB2ENR), r= eg ); HAL_WRITE_UINT32((CYGHWR_HAL_STM32_RCC + CYGHWR_HAL_STM32_RCC_APB2ENR), (reg | (1u << CYGHWR_HAL_STM32_RCC_APB2ENR_TIM1) | (1u << CYGHWR_HAL_STM32_RCC_APB2ENR_TIM8) | (1u << CYGHWR_HAL_STM32_RCC_APB2ENR_TIM9) | (1u << CYGHWR_HAL_STM32_RCC_APB2ENR_TIM10) | (1u << CYGHWR_HAL_STM32_RCC_APB2ENR_TIM11) ) ); #endif } ###########################################################################= ############ This seems to resolve the issue and now the timer test runs reliably and di= splays reasonable looking results, whereas before the results were always 0. Advice on how this initialization would be more correctly done would be app= reciated. <<<<<<<<<<<<<<<<<<<<<<<<<<<< PREVIOUS POST END >>>>>>>>>>>>>>>>>>>>>>>>>>>>= >>>>>>>>>>>>>>>>>> Richard Morris Senior Staff Firmware Engineer Richard Morris Senior Staff Firmware Engineer T 650.638.6883 850 Lincoln Centre Dr MS 407-1 Foster City, CA 94404 USA http://www.lifetechnologies.com -- Before posting, please read the FAQ: http://ecos.sourceware.org/fom/ecos and search the list archive: http://ecos.sourceware.org/ml/ecos-discuss