From mboxrd@z Thu Jan 1 00:00:00 1970 From: Fabrice Gautier To: "'andrew.lunn@ascom.ch'" , msasi@yahoo.com Cc: ecos-discuss@sourceware.cygnus.com Subject: [ECOS] Port of 82559 ethernet driver for PC target (was: "RE: [ECOS] Newbie Question!") Date: Tue, 03 Oct 2000 20:14:00 -0000 Message-id: <8AE4B526B977D411841F00A0CC334020052C81@cuz-exchange.sdesigns.net> X-SW-Source: 2000-10/msg00020.html Hi, > -----Original Message----- > From: andrew.lunn@ascom.ch [ mailto:andrew.lunn@ascom.ch ] > Sent: Friday, September 22, 2000 12:23 AM > > > Hi, > > I am ready to volenteer for doing this. Can someone > > provide me insights into where I can get started. Sasidhar, did you start some work on this yet? > Look back in the email archive. There was a contribution of a PCI > library for the x86. You will need to intergrate this with the current > anoncvs tree. That's should be easy... :-) Just needed to add the HAL_PCI_TRANSLATE_INTERRUPT macro > You then need to get an i82559 card from somewhere. Thats the Intel > Intel EtherExpress Pro. The driver may also work on i82557 and i82558, > but its not been tested and probably needs some tweeking. > > Then make sure the PCI library can find the card. The test program > pci1 should see it. That seems ok for me > Decide where to put the PCI memory window. Change the MMU to support > this. Also watch out for the new heap/malloc code. It may try to put a > heap on the PCI window. Well, Afaik there is no MMU involved in the 386-PC target. It uses a simple 32 bits flat model. So I don't think there is no need to setup a PCI memory window. I think the 3 BAR are setup by the BIOS. I read: BAR[0] 0xE7300000 / probed size 0x00000000 / CPU addr 0xFFFFFFFF BAR[1] 0x0000E801 / probed size 0x00000000 / CPU addr 0xFFFFFFFF BAR[2] 0xE7100000 / probed size 0x00000000 / CPU addr 0xFFFFFFFF So I think thats mean that I can just access the registers through those adresses spaces. (right?) And for the heap/malloc things, I don't understand why there is a special malloc stuff. Why not regular memory pools?. And it seems there is need to set up a region in the memory layout. Why? As I understand how the 82559 works, when we want to send a packet, we have to write the adress of some structure in the SCB General Pointer register (offset 04h) and then a transmit command in the SCB command register. Is that right? If so, the adress we pass can just be anywhere in memory right? Thanks