[ECOS] fix for mpc8xxx cache handling

["Pieter-Jan Busschaert" <pieterjan.busschaert@gmail.com>]

Hello,


We have discovered a problem in the HAL_DCACHE_FLUSH macro for the
mpc8xxx powerpc variant. The same issue is present in the similar
macros HAL_DCACHE_INVALIDATE and HAL_DCACHE_STORE.

Just for reference, here is the current HAL_DCACHE_FLUSH macro :

#define HAL_DCACHE_FLUSH( _base_ , _size_ )                     \
    CYG_MACRO_START                                             \
    cyg_uint32 __base = (cyg_uint32) (_base_);                  \
    cyg_int32 __size = (cyg_int32) (_size_);                    \
    while (__size > 0) {                                        \
        asm volatile ("dcbf 0,%0;sync;" : : "r" (__base));      \
        __base += HAL_DCACHE_LINE_SIZE;                         \
        __size -= HAL_DCACHE_LINE_SIZE;                         \
    }                                                           \
    CYG_MACRO_END


When you want to flush some buffer that spans 2 cache lines (but its
size is smaller than one cache line), only the first cache line will
be flushed. This macro will only work correctly if _base_ is aligned
to the start of a cache line.

It can be fixed by adding this line in front of the while loop :

__size += (__base % HAL_DCACHE_LINE_SIZE);


Before submitting a patch, I'd rather have input about this change :
=> Is the assembler function dcbf supposed to work on non-aligned
addresses (it seems to work here) ?
=> Is the HAL_DCACHE_FLUSH macro supposed to work on non-aligned addresses ?
=> Is this the good way to fix the issue or is there a better alternative ?


greetings,

--
Pieter-Jan Busschaert
Software Engineer
Barco Presentation & Simulation

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