From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 324 invoked by alias); 6 Nov 2007 10:29:42 -0000 Received: (qmail 312 invoked by uid 22791); 6 Nov 2007 10:29:41 -0000 X-Spam-Check-By: sourceware.org Received: from nf-out-0910.google.com (HELO nf-out-0910.google.com) (64.233.182.187) by sourceware.org (qpsmtpd/0.31) with ESMTP; Tue, 06 Nov 2007 10:29:39 +0000 Received: by nf-out-0910.google.com with SMTP id b21so1365830nfd for ; Tue, 06 Nov 2007 02:29:36 -0800 (PST) Received: by 10.78.138.14 with SMTP id l14mr4721694hud.1194344976142; Tue, 06 Nov 2007 02:29:36 -0800 (PST) Received: by 10.78.151.1 with HTTP; Tue, 6 Nov 2007 02:29:36 -0800 (PST) Message-ID: <950a36fb0711060229lee6c6fi7d75eeb6c73e6088@mail.gmail.com> Date: Tue, 06 Nov 2007 10:29:00 -0000 From: "Pieter-Jan Busschaert" To: ecos-discuss@ecos.sourceware.org MIME-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Content-Disposition: inline Mailing-List: contact ecos-discuss-help@ecos.sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: ecos-discuss-owner@ecos.sourceware.org Subject: [ECOS] fix for mpc8xxx cache handling X-SW-Source: 2007-11/txt/msg00025.txt.bz2 Hello, We have discovered a problem in the HAL_DCACHE_FLUSH macro for the mpc8xxx powerpc variant. The same issue is present in the similar macros HAL_DCACHE_INVALIDATE and HAL_DCACHE_STORE. Just for reference, here is the current HAL_DCACHE_FLUSH macro : #define HAL_DCACHE_FLUSH( _base_ , _size_ ) \ CYG_MACRO_START \ cyg_uint32 __base = (cyg_uint32) (_base_); \ cyg_int32 __size = (cyg_int32) (_size_); \ while (__size > 0) { \ asm volatile ("dcbf 0,%0;sync;" : : "r" (__base)); \ __base += HAL_DCACHE_LINE_SIZE; \ __size -= HAL_DCACHE_LINE_SIZE; \ } \ CYG_MACRO_END When you want to flush some buffer that spans 2 cache lines (but its size is smaller than one cache line), only the first cache line will be flushed. This macro will only work correctly if _base_ is aligned to the start of a cache line. It can be fixed by adding this line in front of the while loop : __size += (__base % HAL_DCACHE_LINE_SIZE); Before submitting a patch, I'd rather have input about this change : => Is the assembler function dcbf supposed to work on non-aligned addresses (it seems to work here) ? => Is the HAL_DCACHE_FLUSH macro supposed to work on non-aligned addresses ? => Is this the good way to fix the issue or is there a better alternative ? greetings, -- Pieter-Jan Busschaert Software Engineer Barco Presentation & Simulation -- Before posting, please read the FAQ: http://ecos.sourceware.org/fom/ecos and search the list archive: http://ecos.sourceware.org/ml/ecos-discuss