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From: Danny Sade <danny@channelot.com>
To: Christophe Coutand <ccoutand@stmi.com>,
	"ecos-discuss@ecos.sourceware.org" 
	<ecos-discuss@ecos.sourceware.org>
Subject: RE: [ECOS] Zero vector interrupts (SIVEC=0) on MPC8xxx
Date: Tue, 01 Sep 2009 11:02:00 -0000	[thread overview]
Message-ID: <EDB04F1999D30A4C8CC2FA320B2855451BAA6899@exrad4.ad.rad.co.il> (raw)
In-Reply-To: <D6050C555CC56940A7AF32652283027611DA23@mail2.STMIRV01.COM>

Hi Christophe, 

> what type of CPU are you using?

I'm using 8247 (PowerQUICC II)

> I think the easiest way for you is to map the decrementer interrupt
> (CYGNUM_HAL_INTERRUPT_DECREMENTER) to something else then 0 and change your variant.inc to
> handle it properly until you find the reason for the spurious interrupts.

I wasn't aware to this mapping option. For the mean time I've defined the macro cygpkg_plf_intc_handler
in my plf_regs.h, and I'm using this macro to identify this case and map the zero vector interrupt to some
other vector which I don't use.

In any case, as far as I understand, an ISR for this zero vector interrupt should always be provided since these
Interrupts are asserted during normal operation.

Thanks

Danny

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      reply	other threads:[~2009-09-01 11:02 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2009-09-01  8:21 Danny Sade
2009-09-01  9:34 ` Christophe Coutand
2009-09-01 11:02   ` Danny Sade [this message]

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