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* RE: [ECOS] Question about system bus
@ 2001-06-19  9:38 harri.siirtola
  2001-06-19  9:44 ` HuangQiang
  0 siblings, 1 reply; 12+ messages in thread
From: harri.siirtola @ 2001-06-19  9:38 UTC (permalink / raw)
  To: HuangQiang, eCos, harri.siirtola

At 17:11 19.6.2001 +0100, HuangQiang wrote:
>...
>#define EXTIOBANK	0x02100000
>// define a test address in IO bank 0
>#define EXTIOTEST	((unsigned long *)(EXTIOBANK + 0x0010))
>...
>// read from the ext io
>
>unsigned long k = 0;
>
>while(1)
>{
>   k =  *EXTIOTEST;
>}  // now no CS signal.

Do you have compiler optimization enabled? If yes, you should use
'((volatile unsigned long *)(EXTIOBANK + 0x0010))', otherwise your
assignment gets optimized away. Check the generated assembly code.
	Harri

^ permalink raw reply	[flat|nested] 12+ messages in thread

* RE: [ECOS] Question about system bus
  2001-06-19  9:38 [ECOS] Question about system bus harri.siirtola
@ 2001-06-19  9:44 ` HuangQiang
  0 siblings, 0 replies; 12+ messages in thread
From: HuangQiang @ 2001-06-19  9:44 UTC (permalink / raw)
  To: eCos, harri.siirtola

still no luck with "volatile unsigned long *". Is the read operation
correct?
thanks

-----Original Message-----
From: harri.siirtola@vtt.fi [ mailto:harri.siirtola@vtt.fi ]
Sent: 19 June 2001 17:37
To: HuangQiang; eCos; harri.siirtola@vtt.fi
Subject: RE: [ECOS] Question about system bus


At 17:11 19.6.2001 +0100, HuangQiang wrote:
>...
>#define EXTIOBANK	0x02100000
>// define a test address in IO bank 0
>#define EXTIOTEST	((unsigned long *)(EXTIOBANK + 0x0010))
>...
>// read from the ext io
>
>unsigned long k = 0;
>
>while(1)
>{
>   k =  *EXTIOTEST;
>}  // now no CS signal.

Do you have compiler optimization enabled? If yes, you should use
'((volatile unsigned long *)(EXTIOBANK + 0x0010))', otherwise your
assignment gets optimized away. Check the generated assembly code.
	Harri

^ permalink raw reply	[flat|nested] 12+ messages in thread

* Re: [ECOS] Question about system bus
  2001-06-20  2:06     ` HuangQiang
@ 2001-06-20 11:02       ` Mark Salter
  2001-06-20 11:02       ` Lewin A.R.W. Edwards
  1 sibling, 0 replies; 12+ messages in thread
From: Mark Salter @ 2001-06-20 11:02 UTC (permalink / raw)
  To: jameshq; +Cc: ecos-discuss, jlarmour

>>>>> HuangQiang  writes:

> while writing to the external IO bank0 I can get CS and while reading I
> can't get CS  why?

Is that memory space cached? Maybe the read hits the cache and the
transaction never makes it to the bus.

--Mark

^ permalink raw reply	[flat|nested] 12+ messages in thread

* RE: [ECOS] Question about system bus
  2001-06-20  2:06     ` HuangQiang
  2001-06-20 11:02       ` Mark Salter
@ 2001-06-20 11:02       ` Lewin A.R.W. Edwards
  1 sibling, 0 replies; 12+ messages in thread
From: Lewin A.R.W. Edwards @ 2001-06-20 11:02 UTC (permalink / raw)
  To: HuangQiang, eCos, Jonathan Larmour

>while writing to the external IO bank0 I can get CS and while reading I
>can't get CS  why?

I haven't been following this thread, so excuse me if this has already been 
mentioned, but if your CPU has Dcache then it should be disabled for this 
I/O range; check the MMU tables.


-- Lewin A.R.W. Edwards
Embedded Engineer, Digi-Frame Inc.
Work: http://www.digi-frame.com/
Tel (914) 937-4090 9am-6:30pm M-F ET
Personal: http://www.larwe.com/ http://www.zws.com/

"Far better it is to dare mighty things, to win glorious triumphs, even 
though checkered by failure, than to rank with those poor spirits who 
neither enjoy much nor suffer much, because they live in the gray twilight 
that knows not victory nor defeat."
(Theodore Roosevelt)

^ permalink raw reply	[flat|nested] 12+ messages in thread

* RE: [ECOS] Question about system bus
  2001-06-19 18:59   ` Jonathan Larmour
@ 2001-06-20  2:06     ` HuangQiang
  2001-06-20 11:02       ` Mark Salter
  2001-06-20 11:02       ` Lewin A.R.W. Edwards
  0 siblings, 2 replies; 12+ messages in thread
From: HuangQiang @ 2001-06-20  2:06 UTC (permalink / raw)
  To: eCos, Jonathan Larmour

My assembly code shows:

			*EXTIOTEST = 0x55;	// write to external IO bank0 and I can get CS from it
-	0xc744	<cyg_user_start+268>:		mov	r3, #16		; 0x10
-	0xc748	<cyg_user_start+272>:		add	r3, r3, #34603008	; 0x2100000
-	0xc74c	<cyg_user_start+276>:		mov	r2, #85		; 0x55
-	0xc750	<cyg_user_start+280>:		str	r2, [r3]
	87
	88			k = *EXTIOTEST;	// read from external IO bank0 and I can't get CS from
it
-	0xc754	<cyg_user_start+284>:		mov	r3, #16		; 0x10
-	0xc758	<cyg_user_start+288>:		add	r3, r3, #34603008	; 0x2100000
-	0xc75c	<cyg_user_start+292>:		ldr	r2, [r3]
-	0xc760	<cyg_user_start+296>:		str	r2, [r11, -#16]


while writing to the external IO bank0 I can get CS and while reading I
can't get CS  why?
Thank you!

huang

-----Original Message-----
From: jlarmour@garibaldi.jifvik.org
[ mailto:jlarmour@garibaldi.jifvik.org]On Behalf Of Jonathan Larmour
Sent: 20 June 2001 03:01
To: HuangQiang
Cc: eCos
Subject: Re: [ECOS] Question about system bus


HuangQiang wrote:
>
> while(1)
> {
>    k =  *EXTIOTEST;
> }  // now no CS signal.

You may want to disassemble this function to be sure the right thing is
happening.

Jifl
--
Red Hat, Rustat House, Clifton Road, Cambridge, UK. Tel: +44 (1223) 271062
Maybe this world is another planet's Hell -Aldous Huxley || Opinions==mine
Come to the Red Hat TechWorld open source conference in Brussels!
Keynotes, techie talks and exhibitions    http://www.redhat-techworld.com/

^ permalink raw reply	[flat|nested] 12+ messages in thread

* Re: [ECOS] Question about system bus
  2001-06-19  9:11 ` HuangQiang
@ 2001-06-19 18:59   ` Jonathan Larmour
  2001-06-20  2:06     ` HuangQiang
  0 siblings, 1 reply; 12+ messages in thread
From: Jonathan Larmour @ 2001-06-19 18:59 UTC (permalink / raw)
  To: HuangQiang; +Cc: eCos

HuangQiang wrote:
> 
> while(1)
> {
>    k =  *EXTIOTEST;
> }  // now no CS signal.

You may want to disassemble this function to be sure the right thing is
happening.

Jifl
-- 
Red Hat, Rustat House, Clifton Road, Cambridge, UK. Tel: +44 (1223) 271062
Maybe this world is another planet's Hell -Aldous Huxley || Opinions==mine
Come to the Red Hat TechWorld open source conference in Brussels!
Keynotes, techie talks and exhibitions    http://www.redhat-techworld.com/

^ permalink raw reply	[flat|nested] 12+ messages in thread

* RE: [ECOS] Question about system bus
@ 2001-06-19 10:02 harri.siirtola
  0 siblings, 0 replies; 12+ messages in thread
From: harri.siirtola @ 2001-06-19 10:02 UTC (permalink / raw)
  To: HuangQiang, eCos, harri.siirtola

At 17:43 19.6.2001 +0100, HuangQiang wrote:
>
>still no luck with "volatile unsigned long *". Is the read operation
>correct?
>thanks

Yes it is... no clues any more, sorry. I checked this on my platform (not
E7T) and it produced correct code. Let's see if someone else knows the
solution.
	Harri

^ permalink raw reply	[flat|nested] 12+ messages in thread

* RE: [ECOS] Question about system bus
  2001-06-19  1:55 harri.siirtola
@ 2001-06-19  9:11 ` HuangQiang
  2001-06-19 18:59   ` Jonathan Larmour
  0 siblings, 1 reply; 12+ messages in thread
From: HuangQiang @ 2001-06-19  9:11 UTC (permalink / raw)
  To: eCos, harri.siirtola

It is a External IO Bank for external device to connect to the ARM E7T,
there is no configuration for input or output setting, just like a memory
location, you can either write and read without setting any i/o setting. At
the monent I can get the CS signal while I write out something to the
external IO bank 0 I can get the CS signal, but no CS while reading from ext
io bank 0. the code shows below.
(by the way I am not actually connecting any external device to the EXT IO
Bank0, I just want to test it for the CS signal while reading and writing
from or to the EXT IO BAnk)


#define EXTIOBANK	0x02100000
// define a test address in IO bank 0
#define EXTIOTEST	((unsigned long *)(EXTIOBANK + 0x0010))

// write to the ext io
 while(1)
{
   *EXTIOTEST = 0x55;
}  // there is CS signal appears on the oscilloscope.

// read from the ext io

unsigned long k = 0;

while(1)
{
   k =  *EXTIOTEST;
}  // now no CS signal.


-----Original Message-----
From: ecos-discuss-owner@sources.redhat.com
[ mailto:ecos-discuss-owner@sources.redhat.com]On Behalf Of
harri.siirtola@vtt.fi
Sent: 19 June 2001 09:54
To: HuangQiang; eCos; harri.siirtola@vtt.fi
Subject: RE: [ECOS] Question about system bus


At 09:32 19.6.2001 +0100, HuangQiang wrote:
>But in the source code there "k!=1" ( I check it using the debuger). So if
I
>want to read a data from a memory location how can I use it?
>  by "k = *EXTIOBANK0" or other means?
>When I write the data to the external memory location by "*EXTIOBANK0 = 1"
,
>I can get the CS signal for ext io bank0, while read I can't get the CS
>signal, why? Thank you
>huang

If this really is an I/O port, configuring it as inputs before reading
might be worth trying. Your processor may provide select signals according
to I/O configuration. Of course, in this case you're not getting what you
wrote just before but the states of the input lines (maybe random if not
connected to anything). Anyway, you could test if you get a select signal
like this. BTW, have you connected a FIFO or something to the port? In that
case, you could get what you wrote before...

	Harri

^ permalink raw reply	[flat|nested] 12+ messages in thread

* RE: [ECOS] Question about system bus
@ 2001-06-19  1:55 harri.siirtola
  2001-06-19  9:11 ` HuangQiang
  0 siblings, 1 reply; 12+ messages in thread
From: harri.siirtola @ 2001-06-19  1:55 UTC (permalink / raw)
  To: HuangQiang, eCos, harri.siirtola

At 09:32 19.6.2001 +0100, HuangQiang wrote:
>But in the source code there "k!=1" ( I check it using the debuger). So if I
>want to read a data from a memory location how can I use it?
>  by "k = *EXTIOBANK0" or other means?
>When I write the data to the external memory location by "*EXTIOBANK0 = 1" ,
>I can get the CS signal for ext io bank0, while read I can't get the CS
>signal, why? Thank you
>huang

If this really is an I/O port, configuring it as inputs before reading
might be worth trying. Your processor may provide select signals according
to I/O configuration. Of course, in this case you're not getting what you
wrote just before but the states of the input lines (maybe random if not
connected to anything). Anyway, you could test if you get a select signal
like this. BTW, have you connected a FIFO or something to the port? In that
case, you could get what you wrote before...

	Harri

^ permalink raw reply	[flat|nested] 12+ messages in thread

* RE: [ECOS] Question about system bus
  2001-06-19  0:37 harri.siirtola
@ 2001-06-19  1:33 ` HuangQiang
  0 siblings, 0 replies; 12+ messages in thread
From: HuangQiang @ 2001-06-19  1:33 UTC (permalink / raw)
  To: eCos, harri.siirtola

-----Original Message-----
From: harri.siirtola@vtt.fi [ mailto:harri.siirtola@vtt.fi ]
Sent: 19 June 2001 08:36
To: HuangQiang; eCos
Subject: Re: [ECOS] Question about system bus


At 17:31 18.6.2001 +0100, HuangQiang wrote:
>Hi all:
>...
>e.g.
>    reading from the ext IO
>
>	int k;
>	*EXTIOBANK0 = 1;
>	k = *EXTIOBANK0;
>	// now k is not the same as what I have written to ('1'). why ?

>I don't know of EB7T exactly but in many processors, an I/O port defined as
>an output is write-only. So you must maintain a static variable to hold the
>last value written to the port. You said you're getting proper select
>signals so I suppose your EXTIOBANK0 declaration is ok (otherwise the first
>thing to check).

But in the source code there "k!=1" ( I check it using the debuger). So if I
want to read a data from a memory location how can I use it?
  by "k = *EXTIOBANK0" or other means?
When I write the data to the external memory location by "*EXTIOBANK0 = 1" ,
I can get the CS signal for ext io bank0, while read I can't get the CS
signal, why? Thank you
huang



>
>Thank you
>
>huang

	Harri

^ permalink raw reply	[flat|nested] 12+ messages in thread

* Re: [ECOS] Question about system bus
@ 2001-06-19  0:37 harri.siirtola
  2001-06-19  1:33 ` HuangQiang
  0 siblings, 1 reply; 12+ messages in thread
From: harri.siirtola @ 2001-06-19  0:37 UTC (permalink / raw)
  To: HuangQiang, eCos

At 17:31 18.6.2001 +0100, HuangQiang wrote:
>Hi all:
>...
>e.g.
>    reading from the ext IO
>
>	int k;
>	*EXTIOBANK0 = 1;
>	k = *EXTIOBANK0;
>	// now k is not the same as what I have written to ('1'). why ?

I don't know of EB7T exactly but in many processors, an I/O port defined as
an output is write-only. So you must maintain a static variable to hold the
last value written to the port. You said you're getting proper select
signals so I suppose your EXTIOBANK0 declaration is ok (otherwise the first
thing to check).

>
>Thank you
>
>huang

	Harri

^ permalink raw reply	[flat|nested] 12+ messages in thread

* [ECOS] Question about system bus
@ 2001-06-18  9:31 HuangQiang
  0 siblings, 0 replies; 12+ messages in thread
From: HuangQiang @ 2001-06-18  9:31 UTC (permalink / raw)
  To: eCos

Hi all:
   I am doing system interface with the ARM E7T under eCos. I want to map
the external IO port to memory location 0x0210 0000. I have done it and when
I write a data to ext IO, I can generate the proper selection signal, but
when I read a data from the ext IO nothing happens. Could anybody tell me a
little about reading from the memory under eCos? Is the following code right
or not? Thanks a lot!

e.g.
    reading from the ext IO

	int k;
	*EXTIOBANK0 = 1;
	k = *EXTIOBANK0;
	// now k is not the same as what I have written to ('1'). why ?

Thank you

huang

^ permalink raw reply	[flat|nested] 12+ messages in thread

end of thread, other threads:[~2001-06-20 11:02 UTC | newest]

Thread overview: 12+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2001-06-19  9:38 [ECOS] Question about system bus harri.siirtola
2001-06-19  9:44 ` HuangQiang
  -- strict thread matches above, loose matches on Subject: below --
2001-06-19 10:02 harri.siirtola
2001-06-19  1:55 harri.siirtola
2001-06-19  9:11 ` HuangQiang
2001-06-19 18:59   ` Jonathan Larmour
2001-06-20  2:06     ` HuangQiang
2001-06-20 11:02       ` Mark Salter
2001-06-20 11:02       ` Lewin A.R.W. Edwards
2001-06-19  0:37 harri.siirtola
2001-06-19  1:33 ` HuangQiang
2001-06-18  9:31 HuangQiang

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