From mboxrd@z Thu Jan 1 00:00:00 1970 From: "David Airlie" To: "Sebastien ANDRE" Cc: ecos-discuss@sources.redhat.com Subject: Re: [ECOS] driver for 16x7X serial chip questions Date: Thu, 16 Aug 2001 03:04:00 -0000 Message-id: References: <3B7B7106.AF90D772@sxb.bsf.alcatel.fr> X-SW-Source: 2001-08/msg00536.html All the definitions are from the 16550 data sheet... the names are probably a bit different but they should correspond to the bits in the datasheet.. I don't have at 16x7x datasheet but it may have changed a lot so porting the 16550 driver is not the right way to do it ... from your comments it seems as if a lot has changed... Get the 16550 datasheet read all the register definitions and you'll see what each #define means in that context... the transfer the context to the 16x7x datasheet.. Dave. > > I have some questions about these definitions : > > > // Interrupt Enable Register =====> i don't understand sense of > RCV,XMT,LS,MS , these terms do not appear in the documentation of my chips > specification in the "Interrupt Enable Register" Options > #define IER_RCV 0x01 > #define IER_XMT 0x02 > #define IER_LS 0x04 > #define IER_MS 0x08 > > > // Line Control Register ======> I haven't option like it !! > the only option i can have not use is : Bit 6 set : Break Control Bit = Forces > the transmitter to go low to alert the communication terminal > #define LCR_DL 0x40 // Enable baud rate latch > > // Line Status Register > #define LSR_PE 0x80 // > bit 7 to 1 = 128d = 80h 16x5x = 04h > #define LSR_FE 0x80 // > bit 7 to 1 = 128d = 80h 16x5x = 08h > ==> All the same bit ? they say : At least one parity error,framing error or > breaking error > #define LSR_BI 0x80 // > bit 7 to 1 = 128d = 80h 16x5x = > 10h indication in the RX FIFO. Cleared when no more errors are > present in the FIFO > > #define LSR_TEMT 0x40 I don't > understand this option > #define LSR_FIE 0x80 I > don't understand this option too :-) > > // Modem Control Registerw > #define MCR_DTR 0x01 Don't > understant again, i have these options in this register: xon_en (enable > XON Any function), tcr_tlr and clksel (divide clock by four) > #define MCR_RTS 0x02 > #define MCR_INT 0x08 > > // Interrupt status Register > #define ISR_MS 0x00 // > bit 0 to 0 = 00h 16x5x = 00h > ====> An interrupt is pending ? > #define ISR_nIP 0x01 // > bit 0 to 1 = 01h 16x5x = 01h > ====> No interrupt is pending ? > #define ISR_64BFIFO 0x20 > #define ISR_FIFOworks 0x40 Not match > with my options :-( i have it_type ,fcr_mirror) > #define ISR_FIFOen 0x80 > > // Modem Status Register In my > documentation my chip read this register as zeros then I must make 0 in all > options ? > #define MSR_DCTS 0x00 > #define MSR_DDSR 0x00 > #define MSR_TERI 0x00 > #define MSR_DDCD 0x00 > #define MSR_CTS 0x00 > #define MSR_DSR 0x00 > #define MSR_RI 0x00 > #define MSR_CD 0x00 > > // FIFO Control Register > #define FCR_DMA 0x08 // DMA mode select > #define FCR_F64 0x20 // Enable 64 byte fifo (16750+) > #define FCR_RT14 0xC0 // Set Rx trigger at 14 Don't > Match with options name in my documentation :-( > #define FCR_RT4 0x40 // Set Rx trigger at 4 > #define FCR_RT1 0x00 // Set Rx trigger at 1 > > So i have another probleme, The base adress for these register is FFFF:0800 > but where you defined it ? > It' here =========> ???? > in > "/opt/ecos/ecos-1.3.1/packages/devs/serial/arm/ipphone/current/include/arm_arm7_ipphone_ser.inl" > > static pc_serial_info ipphone_serial_info0 = {0x0D800000, > > CYGNUM_HAL_INTERRUPT_SERIALA}; > > > So i'm sorry for this long mail then i continue to search :-) > > > Sebastien. > best regards. > > > > > > -- David Airlie, Software Engineer, Parthus Technologies plc., Mary Rosse Centre, National Tech Park, Limerick, Ireland. t: +353-61-508116 / f: +353-61-508101 / David.Airlie@parthus.com