Index: devs/eth/powerpc/quicc/current/src/if_quicc.c =================================================================== RCS file: /home/cvs/ecc/ecc/devs/eth/powerpc/quicc/current/src/if_quicc.c,v retrieving revision 1.5 diff -u -5 -p -r1.5 if_quicc.c --- devs/eth/powerpc/quicc/current/src/if_quicc.c 2000/10/24 10:28:33 1.5 +++ devs/eth/powerpc/quicc/current/src/if_quicc.c 2000/12/27 23:27:26 @@ -79,10 +79,22 @@ static unsigned char quicc_eth_rxbufs[CY static unsigned char quicc_eth_txbufs[CYGNUM_DEVS_ETH_POWERPC_QUICC_TxNUM] [CYGNUM_DEVS_ETH_POWERPC_QUICC_BUFSIZE]; static struct quicc_eth_info quicc_eth0_info; static unsigned char enaddr[] = { 0x08, 0x00, 0x3E, 0x28, 0x79, 0xB8}; +#ifdef CYGPKG_REDBOOT +#include +#ifdef CYGSEM_REDBOOT_FLASH_CONFIG +#include +#include +RedBoot_config_option("Network hardware address [MAC]", + quicc_esa, + ALWAYS_ENABLED, true, + CONFIG_ESA + ); +#endif +#endif ETH_DRV_SC(quicc_eth0_sc, &quicc_eth0_info, // Driver specific data "eth0", // Name for this interface quicc_eth_start, @@ -134,20 +146,32 @@ quicc_eth_init(struct cyg_netdevtab_entr { struct eth_drv_sc *sc = (struct eth_drv_sc *)tab->device_instance; struct quicc_eth_info *qi = (struct quicc_eth_info *)sc->driver_private; volatile EPPC *eppc = (volatile EPPC *)eppc_base(); struct cp_bufdesc *rxbd, *txbd; - unsigned char *RxBUF, *TxBUF, *ep, *ap; + unsigned char *RxBUF, *TxBUF, *ep, *ap; volatile struct ethernet_pram *enet_pram; volatile struct scc_regs *scc; int TxBD, RxBD; int cache_state; int i; // Fetch the board address from the VPD #define VPD_ETHERNET_ADDRESS 0x08 - _mbx_fetch_VPD(VPD_ETHERNET_ADDRESS, enaddr, sizeof(enaddr)); + if (_mbx_fetch_VPD(VPD_ETHERNET_ADDRESS, enaddr, sizeof(enaddr)) == 0) { +#if defined(CYGPKG_REDBOOT) && \ + defined(CYGSEM_REDBOOT_FLASH_CONFIG) + flash_get_config("quicc_esa", enaddr, CONFIG_ESA); +#else + enet_pram = &eppc->pram[0].enet_scc; + ap = &enaddr[sizeof(enaddr)]; + ep = (unsigned char *)&enet_pram->paddr_h; + for (i = 0; i < sizeof(enaddr); i++) { + *ap++ = *--ep; + } +#endif + } // Ensure consistent state between cache and what the QUICC sees HAL_DCACHE_IS_ENABLED(cache_state); HAL_DCACHE_SYNC(); HAL_DCACHE_DISABLE();